Xenomai  3.1
rt2500pci.h
1 /* rt2500pci.h
2  *
3  * Copyright (C) 2004 - 2005 rt2x00-2.0.0-b3 SourceForge Project
4  * <http://rt2x00.serialmonkey.com>
5  * 2006 rtnet adaption by Daniel Gregorek
6  * <dxg@gmx.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the
20  * Free Software Foundation, Inc.,
21  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22  */
23 
24 /*
25  * Module: rt2500pci
26  * Abstract: Data structures and registers for the rt2500pci module.
27  * Supported chipsets: RT2560.
28  */
29 
30 #ifndef RT2500PCI_H
31 #define RT2500PCI_H
32 
33 /*
34  * RT chip defines
35  */
36 #define RT2560 0x0201
37 
38 /*
39  * RF chip defines
40  */
41 #define RF2522 0x0200
42 #define RF2523 0x0201
43 #define RF2524 0x0202
44 #define RF2525 0x0203
45 #define RF2525E 0x0204
46 #define RF5222 0x0210
47 
48 /*
49  * Control/Status Registers(CSR).
50  */
51 #define CSR0 0x0000 /* ASIC revision number. */
52 #define CSR1 0x0004 /* System control register. */
53 #define CSR2 0x0008 /* System admin status register (invalid). */
54 #define CSR3 0x000c /* STA MAC address register 0. */
55 #define CSR4 0x0010 /* STA MAC address register 1. */
56 #define CSR5 0x0014 /* BSSID register 0. */
57 #define CSR6 0x0018 /* BSSID register 1. */
58 #define CSR7 0x001c /* Interrupt source register. */
59 #define CSR8 0x0020 /* Interrupt mask register. */
60 #define CSR9 0x0024 /* Maximum frame length register. */
61 #define SECCSR0 0x0028 /* WEP control register. */
62 #define CSR11 0x002c /* Back-off control register. */
63 #define CSR12 0x0030 /* Synchronization configuration register 0. */
64 #define CSR13 0x0034 /* Synchronization configuration register 1. */
65 #define CSR14 0x0038 /* Synchronization control register. */
66 #define CSR15 0x003c /* Synchronization status register. */
67 #define CSR16 0x0040 /* TSF timer register 0. */
68 #define CSR17 0x0044 /* TSF timer register 1. */
69 #define CSR18 0x0048 /* IFS timer register 0. */
70 #define CSR19 0x004c /* IFS timer register 1. */
71 #define CSR20 0x0050 /* WakeUp register. */
72 #define CSR21 0x0054 /* EEPROM control register. */
73 #define CSR22 0x0058 /* CFP Control Register. */
74 
75 /*
76  * Transmit related CSRs.
77  */
78 #define TXCSR0 0x0060 /* TX control register. */
79 #define TXCSR1 0x0064 /* TX configuration register. */
80 #define TXCSR2 0x0068 /* TX descriptor configuratioon register. */
81 #define TXCSR3 0x006c /* TX Ring Base address register. */
82 #define TXCSR4 0x0070 /* TX Atim Ring Base address register. */
83 #define TXCSR5 0x0074 /* TX Prio Ring Base address register. */
84 #define TXCSR6 0x0078 /* Beacon base address. */
85 #define TXCSR7 0x007c /* AutoResponder Control Register. */
86 #define TXCSR8 0x0098 /* CCK TX BBP registers. */
87 #define TXCSR9 0x0094 /* OFDM TX BBP registers. */
88 
89 /*
90  * Receive related CSRs.
91  */
92 #define RXCSR0 0x0080 /* RX control register. */
93 #define RXCSR1 0x0084 /* RX descriptor configuration register. */
94 #define RXCSR2 0x0088 /* RX Ring base address register. */
95 #define RXCSR3 0x0090 /* BBP ID register 0 */
96 #define ARCSR1 0x009c /* Auto Responder PLCP config register 1. */
97 
98 /*
99  * PCI control CSRs.
100  */
101 #define PCICSR 0x008c /* PCI control register. */
102 
103 /*
104  * Statistic Register.
105  */
106 #define CNT0 0x00a0 /* FCS error count. */
107 #define TIMECSR2 0x00a8
108 #define CNT1 0x00ac /* PLCP error count. */
109 #define CNT2 0x00b0 /* long error count. */
110 #define TIMECSR3 0x00b4
111 #define CNT3 0x00b8 /* CCA false alarm count. */
112 #define CNT4 0x00bc /* Rx FIFO overflow count. */
113 #define CNT5 0x00c0 /* Tx FIFO underrun count. */
114 
115 /*
116  * Baseband Control Register.
117  */
118 #define PWRCSR0 0x00c4 /* Power mode configuration. */
119 #define PSCSR0 0x00c8 /* Power state transition time. */
120 #define PSCSR1 0x00cc /* Power state transition time. */
121 #define PSCSR2 0x00d0 /* Power state transition time. */
122 #define PSCSR3 0x00d4 /* Power state transition time. */
123 #define PWRCSR1 0x00d8 /* Manual power control / status. */
124 #define TIMECSR 0x00dc /* Timer control. */
125 #define MACCSR0 0x00e0 /* MAC configuration. */
126 #define MACCSR1 0x00e4 /* MAC configuration. */
127 #define RALINKCSR 0x00e8 /* Ralink Auto-reset register. */
128 #define BCNCSR 0x00ec /* Beacon interval control register. */
129 
130 /*
131  * BBP / RF / IF Control Register.
132  */
133 #define BBPCSR 0x00f0 /* BBP serial control. */
134 #define RFCSR 0x00f4 /* RF serial control. */
135 #define LEDCSR 0x00f8 /* LED control register */
136 
137 #define SECCSR3 0x00fc /* AES control register. */
138 
139 /*
140  * ASIC pointer information.
141  */
142 #define RXPTR 0x0100 /* Current RX ring address. */
143 #define TXPTR 0x0104 /* Current Tx ring address. */
144 #define PRIPTR 0x0108 /* Current Priority ring address. */
145 #define ATIMPTR 0x010c /* Current ATIM ring address. */
146 
147 #define TXACKCSR0 0x0110 /* TX ACK timeout. */
148 #define ACKCNT0 0x0114 /* TX ACK timeout count. */
149 #define ACKCNT1 0x0118 /* RX ACK timeout count. */
150 
151 /*
152  * GPIO and others.
153  */
154 #define GPIOCSR 0x0120 /* GPIO. */
155 #define FIFOCSR0 0x0128 /* TX FIFO pointer. */
156 #define FIFOCSR1 0x012c /* RX FIFO pointer. */
157 #define BCNCSR1 0x0130 /* Tx BEACON offset time, unit: 1 usec. */
158 #define MACCSR2 0x0134 /* TX_PE to RX_PE delay time, unit: 1 PCI clock cycle. */
159 #define TESTCSR 0x0138 /* TEST mode selection register. */
160 #define ARCSR2 0x013c /* 1 Mbps ACK/CTS PLCP. */
161 #define ARCSR3 0x0140 /* 2 Mbps ACK/CTS PLCP. */
162 #define ARCSR4 0x0144 /* 5.5 Mbps ACK/CTS PLCP. */
163 #define ARCSR5 0x0148 /* 11 Mbps ACK/CTS PLCP. */
164 #define ARTCSR0 0x014c /* ACK/CTS payload consumed time for 1/2/5.5/11 mbps. */
165 #define ARTCSR1 \
166  0x0150 /* OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. */
167 #define ARTCSR2 \
168  0x0154 /* OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. */
169 #define SECCSR1 0x0158 /* WEP control register. */
170 #define BBPCSR1 0x015c /* BBP TX configuration. */
171 #define DBANDCSR0 0x0160 /* Dual band configuration register 0. */
172 #define DBANDCSR1 0x0164 /* Dual band configuration register 1. */
173 #define BBPPCSR 0x0168 /* BBP Pin control register. */
174 #define DBGSEL0 0x016c /* MAC special debug mode selection register 0. */
175 #define DBGSEL1 0x0170 /* MAC special debug mode selection register 1. */
176 #define BISTCSR 0x0174 /* BBP BIST register. */
177 #define MCAST0 0x0178 /* multicast filter register 0. */
178 #define MCAST1 0x017c /* multicast filter register 1. */
179 #define UARTCSR0 0x0180 /* UART1 TX register. */
180 #define UARTCSR1 0x0184 /* UART1 RX register. */
181 #define UARTCSR3 0x0188 /* UART1 frame control register. */
182 #define UARTCSR4 0x018c /* UART1 buffer control register. */
183 #define UART2CSR0 0x0190 /* UART2 TX register. */
184 #define UART2CSR1 0x0194 /* UART2 RX register. */
185 #define UART2CSR3 0x0198 /* UART2 frame control register. */
186 #define UART2CSR4 0x019c /* UART2 buffer control register. */
187 
188 /*
189  * EEPROM addresses
190  */
191 #define EEPROM_ANTENNA 0x10
192 #define EEPROM_GEOGRAPHY 0x12
193 #define EEPROM_BBP_START 0x13
194 #define EEPROM_BBP_END 0x22
195 
196 #define EEPROM_BBP_SIZE 16
197 
198 /*
199  * CSR Registers.
200  * Some values are set in TU, whereas 1 TU == 1024 us.
201  */
202 
203 /*
204  * CSR1: System control register.
205  */
206 #define CSR1_SOFT_RESET \
207  FIELD32(0, 0x00000001) /* Software reset, 1: reset, 0: normal. */
208 #define CSR1_BBP_RESET \
209  FIELD32(1, 0x00000002) /* Hardware reset, 1: reset, 0, release. */
210 #define CSR1_HOST_READY \
211  FIELD32(2, 0x00000004) /* Host ready after initialization. */
212 
213 /*
214  * CSR3: STA MAC address register 0.
215  */
216 #define CSR3_BYTE0 FIELD32(0, 0x000000ff) /* MAC address byte 0. */
217 #define CSR3_BYTE1 FIELD32(8, 0x0000ff00) /* MAC address byte 1. */
218 #define CSR3_BYTE2 FIELD32(16, 0x00ff0000) /* MAC address byte 2. */
219 #define CSR3_BYTE3 FIELD32(24, 0xff000000) /* MAC address byte 3. */
220 
221 /*
222  * CSR4: STA MAC address register 1.
223  */
224 #define CSR4_BYTE4 FIELD32(0, 0x000000ff) /* MAC address byte 4. */
225 #define CSR4_BYTE5 FIELD32(8, 0x0000ff00) /* MAC address byte 5. */
226 
227 /*
228  * CSR5: BSSID register 0.
229  */
230 #define CSR5_BYTE0 FIELD32(0, 0x000000ff) /* BSSID address byte 0. */
231 #define CSR5_BYTE1 FIELD32(8, 0x0000ff00) /* BSSID address byte 1. */
232 #define CSR5_BYTE2 FIELD32(16, 0x00ff0000) /* BSSID address byte 2. */
233 #define CSR5_BYTE3 FIELD32(24, 0xff000000) /* BSSID address byte 3. */
234 
235 /*
236  * CSR6: BSSID register 1.
237  */
238 #define CSR6_BYTE4 FIELD32(0, 0x000000ff) /* BSSID address byte 4. */
239 #define CSR6_BYTE5 FIELD32(8, 0x0000ff00) /* BSSID address byte 5. */
240 
241 /*
242  * CSR7: Interrupt source register.
243  * Write 1 to clear.
244  */
245 #define CSR7_TBCN_EXPIRE \
246  FIELD32(0, 0x00000001) /* beacon timer expired interrupt. */
247 #define CSR7_TWAKE_EXPIRE \
248  FIELD32(1, 0x00000002) /* wakeup timer expired interrupt. */
249 #define CSR7_TATIMW_EXPIRE \
250  FIELD32(2, 0x00000004) /* timer of atim window expired interrupt. */
251 #define CSR7_TXDONE_TXRING \
252  FIELD32(3, 0x00000008) /* tx ring transmit done interrupt. */
253 #define CSR7_TXDONE_ATIMRING \
254  FIELD32(4, 0x00000010) /* atim ring transmit done interrupt. */
255 #define CSR7_TXDONE_PRIORING \
256  FIELD32(5, 0x00000020) /* priority ring transmit done interrupt. */
257 #define CSR7_RXDONE FIELD32(6, 0x00000040) /* receive done interrupt. */
258 #define CSR7_DECRYPTION_DONE \
259  FIELD32(7, 0x00000080) /* Decryption done interrupt. */
260 #define CSR7_ENCRYPTION_DONE \
261  FIELD32(8, 0x00000100) /* Encryption done interrupt. */
262 #define CSR7_UART1_TX_TRESHOLD \
263  FIELD32(9, 0x00000200) /* UART1 TX reaches threshold. */
264 #define CSR7_UART1_RX_TRESHOLD \
265  FIELD32(10, 0x00000400) /* UART1 RX reaches threshold. */
266 #define CSR7_UART1_IDLE_TRESHOLD \
267  FIELD32(11, 0x00000800) /* UART1 IDLE over threshold. */
268 #define CSR7_UART1_TX_BUFF_ERROR \
269  FIELD32(12, 0x00001000) /* UART1 TX buffer error. */
270 #define CSR7_UART1_RX_BUFF_ERROR \
271  FIELD32(13, 0x00002000) /* UART1 RX buffer error. */
272 #define CSR7_UART2_TX_TRESHOLD \
273  FIELD32(14, 0x00004000) /* UART2 TX reaches threshold. */
274 #define CSR7_UART2_RX_TRESHOLD \
275  FIELD32(15, 0x00008000) /* UART2 RX reaches threshold. */
276 #define CSR7_UART2_IDLE_TRESHOLD \
277  FIELD32(16, 0x00010000) /* UART2 IDLE over threshold. */
278 #define CSR7_UART2_TX_BUFF_ERROR \
279  FIELD32(17, 0x00020000) /* UART2 TX buffer error. */
280 #define CSR7_UART2_RX_BUFF_ERROR \
281  FIELD32(18, 0x00040000) /* UART2 RX buffer error. */
282 #define CSR7_TIMER_CSR3_EXPIRE \
283  FIELD32(19, \
284  0x00080000) /* TIMECSR3 timer expired (802.1H quiet period). */
285 
286 /*
287  * CSR8: Interrupt mask register.
288  * Write 1 to mask interrupt.
289  */
290 #define CSR8_TBCN_EXPIRE \
291  FIELD32(0, 0x00000001) /* beacon timer expired interrupt. */
292 #define CSR8_TWAKE_EXPIRE \
293  FIELD32(1, 0x00000002) /* wakeup timer expired interrupt. */
294 #define CSR8_TATIMW_EXPIRE \
295  FIELD32(2, 0x00000004) /* timer of atim window expired interrupt. */
296 #define CSR8_TXDONE_TXRING \
297  FIELD32(3, 0x00000008) /* tx ring transmit done interrupt. */
298 #define CSR8_TXDONE_ATIMRING \
299  FIELD32(4, 0x00000010) /* atim ring transmit done interrupt. */
300 #define CSR8_TXDONE_PRIORING \
301  FIELD32(5, 0x00000020) /* priority ring transmit done interrupt. */
302 #define CSR8_RXDONE FIELD32(6, 0x00000040) /* receive done interrupt. */
303 #define CSR8_DECRYPTION_DONE \
304  FIELD32(7, 0x00000080) /* Decryption done interrupt. */
305 #define CSR8_ENCRYPTION_DONE \
306  FIELD32(8, 0x00000100) /* Encryption done interrupt. */
307 #define CSR8_UART1_TX_TRESHOLD \
308  FIELD32(9, 0x00000200) /* UART1 TX reaches threshold. */
309 #define CSR8_UART1_RX_TRESHOLD \
310  FIELD32(10, 0x00000400) /* UART1 RX reaches threshold. */
311 #define CSR8_UART1_IDLE_TRESHOLD \
312  FIELD32(11, 0x00000800) /* UART1 IDLE over threshold. */
313 #define CSR8_UART1_TX_BUFF_ERROR \
314  FIELD32(12, 0x00001000) /* UART1 TX buffer error. */
315 #define CSR8_UART1_RX_BUFF_ERROR \
316  FIELD32(13, 0x00002000) /* UART1 RX buffer error. */
317 #define CSR8_UART2_TX_TRESHOLD \
318  FIELD32(14, 0x00004000) /* UART2 TX reaches threshold. */
319 #define CSR8_UART2_RX_TRESHOLD \
320  FIELD32(15, 0x00008000) /* UART2 RX reaches threshold. */
321 #define CSR8_UART2_IDLE_TRESHOLD \
322  FIELD32(16, 0x00010000) /* UART2 IDLE over threshold. */
323 #define CSR8_UART2_TX_BUFF_ERROR \
324  FIELD32(17, 0x00020000) /* UART2 TX buffer error. */
325 #define CSR8_UART2_RX_BUFF_ERROR \
326  FIELD32(18, 0x00040000) /* UART2 RX buffer error. */
327 #define CSR8_TIMER_CSR3_EXPIRE \
328  FIELD32(19, \
329  0x00080000) /* TIMECSR3 timer expired (802.1H quiet period). */
330 
331 /*
332  * CSR9: Maximum frame length register.
333  */
334 #define CSR9_MAX_FRAME_UNIT \
335  FIELD32(7, \
336  0x00000f80) /* maximum frame length in 128b unit, default: 12. */
337 
338 /*
339  * SECCSR0: WEP control register.
340  */
341 #define SECCSR0_KICK_DECRYPT \
342  FIELD32(0, 0x00000001) /* Kick decryption engine, self-clear. */
343 #define SECCSR0_ONE_SHOT \
344  FIELD32(1, 0x00000002) /* 0: ring mode, 1: One shot only mode. */
345 #define SECCSR0_DESC_ADDRESS \
346  FIELD32(2, 0xfffffffc) /* Descriptor physical address of frame. */
347 
348 /*
349  * CSR11: Back-off control register.
350  */
351 #define CSR11_CWMIN \
352  FIELD32(0, 0x0000000f) /* CWmin. Default cwmin is 31 (2^5 - 1). */
353 #define CSR11_CWMAX \
354  FIELD32(4, 0x000000f0) /* CWmax. Default cwmax is 1023 (2^10 - 1). */
355 #define CSR11_SLOT_TIME \
356  FIELD32(8, 0x00001f00) /* slot time, default is 20us for 802.11b */
357 #define CSR11_CW_SELECT \
358  FIELD32(13, \
359  0x00002000) /* CWmin/CWmax selection, 1: Register, 0: TXD. */
360 #define CSR11_LONG_RETRY FIELD32(16, 0x00ff0000) /* long retry count. */
361 #define CSR11_SHORT_RETRY FIELD32(24, 0xff000000) /* short retry count. */
362 
363 /*
364  * CSR12: Synchronization configuration register 0.
365  * All units in 1/16 TU.
366  */
367 #define CSR12_BEACON_INTERVAL \
368  FIELD32(0, 0x0000ffff) /* beacon interval, default is 100 TU. */
369 #define CSR12_CFPMAX_DURATION \
370  FIELD32(16, 0xffff0000) /* cfp maximum duration, default is 100 TU. */
371 
372 /*
373  * CSR13: Synchronization configuration register 1.
374  * All units in 1/16 TU.
375  */
376 #define CSR13_ATIMW_DURATION FIELD32(0, 0x0000ffff) /* atim window duration. */
377 #define CSR13_CFP_PERIOD \
378  FIELD32(16, 0x00ff0000) /* cfp period, default is 0 TU. */
379 
380 /*
381  * CSR14: Synchronization control register.
382  */
383 #define CSR14_TSF_COUNT FIELD32(0, 0x00000001) /* enable tsf auto counting. */
384 #define CSR14_TSF_SYNC \
385  FIELD32(1, \
386  0x00000006) /* tsf sync, 0: disable, 1: infra, 2: ad-hoc mode. */
387 #define CSR14_TBCN FIELD32(3, 0x00000008) /* enable tbcn with reload value. */
388 #define CSR14_TCFP \
389  FIELD32(4, 0x00000010) /* enable tcfp & cfp / cp switching. */
390 #define CSR14_TATIMW \
391  FIELD32(5, 0x00000020) /* enable tatimw & atim window switching. */
392 #define CSR14_BEACON_GEN FIELD32(6, 0x00000040) /* enable beacon generator. */
393 #define CSR14_CFP_COUNT_PRELOAD \
394  FIELD32(8, 0x0000ff00) /* cfp count preload value. */
395 #define CSR14_TBCM_PRELOAD \
396  FIELD32(16, 0xffff0000) /* tbcn preload value in units of 64us. */
397 
398 /*
399  * CSR15: Synchronization status register.
400  */
401 #define CSR15_CFP \
402  FIELD32(0, 0x00000001) /* ASIC is in contention-free period. */
403 #define CSR15_ATIMW FIELD32(1, 0x00000002) /* ASIC is in ATIM window. */
404 #define CSR15_BEACON_SENT FIELD32(2, 0x00000004) /* Beacon is send. */
405 
406 /*
407  * CSR16: TSF timer register 0.
408  */
409 #define CSR16_LOW_TSFTIMER FIELD32(0, 0xffffffff)
410 
411 /*
412  * CSR17: TSF timer register 1.
413  */
414 #define CSR17_HIGH_TSFTIMER FIELD32(0, 0xffffffff)
415 
416 /*
417  * CSR18: IFS timer register 0.
418  */
419 #define CSR18_SIFS FIELD32(0, 0x000001ff) /* sifs, default is 10 us. */
420 #define CSR18_PIFS FIELD32(16, 0x01f00000) /* pifs, default is 30 us. */
421 
422 /*
423  * CSR19: IFS timer register 1.
424  */
425 #define CSR19_DIFS FIELD32(0, 0x0000ffff) /* difs, default is 50 us. */
426 #define CSR19_EIFS FIELD32(16, 0xffff0000) /* eifs, default is 364 us. */
427 
428 /*
429  * CSR20: Wakeup timer register.
430  */
431 #define CSR20_DELAY_AFTER_TBCN \
432  FIELD32(0, \
433  0x0000ffff) /* delay after tbcn expired in units of 1/16 TU. */
434 #define CSR20_TBCN_BEFORE_WAKEUP \
435  FIELD32(16, 0x00ff0000) /* number of beacon before wakeup. */
436 #define CSR20_AUTOWAKE \
437  FIELD32(24, 0x01000000) /* enable auto wakeup / sleep mechanism. */
438 
439 /*
440  * CSR21: EEPROM control register.
441  */
442 #define CSR21_RELOAD \
443  FIELD32(0, 0x00000001) /* Write 1 to reload eeprom content. */
444 #define CSR21_EEPROM_DATA_CLOCK FIELD32(1, 0x00000002)
445 #define CSR21_EEPROM_CHIP_SELECT FIELD32(2, 0x00000004)
446 #define CSR21_EEPROM_DATA_IN FIELD32(3, 0x00000008)
447 #define CSR21_EEPROM_DATA_OUT FIELD32(4, 0x00000010)
448 #define CSR21_TYPE_93C46 FIELD32(5, 0x00000020) /* 1: 93c46, 0:93c66. */
449 
450 /*
451  * CSR22: CFP control register.
452  */
453 #define CSR22_CFP_DURATION_REMAIN \
454  FIELD32(0, 0x0000ffff) /* cfp duration remain, in units of TU. */
455 #define CSR22_RELOAD_CFP_DURATION \
456  FIELD32(16, 0x00010000) /* Write 1 to reload cfp duration remain. */
457 
458 /*
459  * TX / RX Registers.
460  * Some values are set in TU, whereas 1 TU == 1024 us.
461  */
462 
463 /*
464  * TXCSR0: TX Control Register.
465  */
466 #define TXCSR0_KICK_TX FIELD32(0, 0x00000001) /* kick tx ring. */
467 #define TXCSR0_KICK_ATIM FIELD32(1, 0x00000002) /* kick atim ring. */
468 #define TXCSR0_KICK_PRIO FIELD32(2, 0x00000004) /* kick priority ring. */
469 #define TXCSR0_ABORT \
470  FIELD32(3, 0x00000008) /* abort all transmit related ring operation. */
471 
472 /*
473  * TXCSR1: TX Configuration Register.
474  */
475 #define TXCSR1_ACK_TIMEOUT \
476  FIELD32(0, \
477  0x000001ff) /* ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. */
478 #define TXCSR1_ACK_CONSUME_TIME \
479  FIELD32(9, \
480  0x0003fe00) /* ack consume time, default = sifs + acktime @ 1mbps. */
481 #define TXCSR1_TSF_OFFSET FIELD32(18, 0x00fc0000) /* insert tsf offset. */
482 #define TXCSR1_AUTORESPONDER \
483  FIELD32(24, \
484  0x01000000) /* enable auto responder which include ack & cts. */
485 
486 /*
487  * TXCSR2: Tx descriptor configuration register.
488  */
489 #define TXCSR2_TXD_SIZE \
490  FIELD32(0, 0x000000ff) /* tx descriptor size, default is 48. */
491 #define TXCSR2_NUM_TXD FIELD32(8, 0x0000ff00) /* number of txd in ring. */
492 #define TXCSR2_NUM_ATIM FIELD32(16, 0x00ff0000) /* number of atim in ring. */
493 #define TXCSR2_NUM_PRIO \
494  FIELD32(24, 0xff000000) /* number of priority in ring. */
495 
496 /*
497  * TXCSR3: TX Ring Base address register.
498  */
499 #define TXCSR3_TX_RING_REGISTER FIELD32(0, 0xffffffff)
500 
501 /*
502  * TXCSR4: TX Atim Ring Base address register.
503  */
504 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0, 0xffffffff)
505 
506 /*
507  * TXCSR5: TX Prio Ring Base address register.
508  */
509 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0, 0xffffffff)
510 
511 /*
512  * TXCSR6: Beacon Base address register.
513  */
514 #define TXCSR6_BEACON_REGISTER FIELD32(0, 0xffffffff)
515 
516 /*
517  * TXCSR7: Auto responder control register.
518  */
519 #define TXCSR7_AR_POWERMANAGEMENT \
520  FIELD32(0, 0x00000001) /* auto responder power management bit. */
521 
522 /*
523  * TXCSR8: CCK Tx BBP register.
524  */
525 #define TXCSR8_CCK_SIGNAL \
526  FIELD32(0, 0x000000ff) /* BBP rate field address for CCK. */
527 #define TXCSR8_CCK_SERVICE \
528  FIELD32(8, 0x0000ff00) /* BBP service field address for CCK. */
529 #define TXCSR8_CCK_LENGTH_LOW \
530  FIELD32(16, 0x00ff0000) /* BBP length low byte address for CCK. */
531 #define TXCSR8_CCK_LENGTH_HIGH \
532  FIELD32(24, 0xff000000) /* BBP length high byte address for CCK. */
533 
534 /*
535  * TXCSR9: OFDM TX BBP registers
536  */
537 #define TXCSR9_OFDM_RATE \
538  FIELD32(0, 0x000000ff) /* BBP rate field address for OFDM. */
539 #define TXCSR9_OFDM_SERVICE \
540  FIELD32(8, 0x0000ff00) /* BBP service field address for OFDM. */
541 #define TXCSR9_OFDM_LENGTH_LOW \
542  FIELD32(16, 0x00ff0000) /* BBP length low byte address for OFDM. */
543 #define TXCSR9_OFDM_LENGTH_HIGH \
544  FIELD32(24, 0xff000000) /* BBP length high byte address for OFDM. */
545 
546 /*
547  * RXCSR0: RX Control Register.
548  */
549 #define RXCSR0_DISABLE_RX FIELD32(0, 0x00000001) /* disable rx engine. */
550 #define RXCSR0_DROP_CRC FIELD32(1, 0x00000002) /* drop crc error. */
551 #define RXCSR0_DROP_PHYSICAL FIELD32(2, 0x00000004) /* drop physical error. */
552 #define RXCSR0_DROP_CONTROL FIELD32(3, 0x00000008) /* drop control frame. */
553 #define RXCSR0_DROP_NOT_TO_ME \
554  FIELD32(4, 0x00000010) /* drop not to me unicast frame. */
555 #define RXCSR0_DROP_TODS \
556  FIELD32(5, 0x00000020) /* drop frame tods bit is true. */
557 #define RXCSR0_DROP_VERSION_ERROR \
558  FIELD32(6, 0x00000040) /* drop version error frame. */
559 #define RXCSR0_PASS_CRC \
560  FIELD32(7, 0x00000080) /* pass all packets with crc attached. */
561 #define RXCSR0_PASS_PLCP \
562  FIELD32(8, \
563  0x00000100) /* Pass all packets with 4 bytes PLCP attached. */
564 #define RXCSR0_DROP_MCAST FIELD32(9, 0x00000200) /* Drop multicast frames. */
565 #define RXCSR0_DROP_BCAST FIELD32(10, 0x00000400) /* Drop broadcast frames. */
566 #define RXCSR0_ENABLE_QOS \
567  FIELD32(11, 0x00000800) /* Accept QOS data frame and parse QOS field. */
568 
569 /*
570  * RXCSR1: RX descriptor configuration register.
571  */
572 #define RXCSR1_RXD_SIZE \
573  FIELD32(0, 0x000000ff) /* rx descriptor size, default is 32b. */
574 #define RXCSR1_NUM_RXD FIELD32(8, 0x0000ff00) /* number of rxd in ring. */
575 
576 /*
577  * RXCSR2: RX Ring base address register.
578  */
579 #define RXCSR2_RX_RING_REGISTER FIELD32(0, 0xffffffff)
580 
581 /*
582  * RXCSR3: BBP ID register for Rx operation.
583  */
584 #define RXCSR3_BBP_ID0 FIELD32(0, 0x0000007f) /* bbp register 0 id. */
585 #define RXCSR3_BBP_ID0_VALID \
586  FIELD32(7, 0x00000080) /* bbp register 0 id is valid or not. */
587 #define RXCSR3_BBP_ID1 FIELD32(8, 0x00007f00) /* bbp register 1 id. */
588 #define RXCSR3_BBP_ID1_VALID \
589  FIELD32(15, 0x00008000) /* bbp register 1 id is valid or not. */
590 #define RXCSR3_BBP_ID2 FIELD32(16, 0x007f0000) /* bbp register 2 id. */
591 #define RXCSR3_BBP_ID2_VALID \
592  FIELD32(23, 0x00800000) /* bbp register 2 id is valid or not. */
593 #define RXCSR3_BBP_ID3 FIELD32(24, 0x7f000000) /* bbp register 3 id. */
594 #define RXCSR3_BBP_ID3_VALID \
595  FIELD32(31, 0x80000000) /* bbp register 3 id is valid or not. */
596 
597 /*
598  * ARCSR1: Auto Responder PLCP config register 1.
599  */
600 #define ARCSR1_AR_BBP_DATA2 \
601  FIELD32(0, 0x000000ff) /* Auto responder BBP register 2 data. */
602 #define ARCSR1_AR_BBP_ID2 \
603  FIELD32(8, 0x0000ff00) /* Auto responder BBP register 2 Id. */
604 #define ARCSR1_AR_BBP_DATA3 \
605  FIELD32(16, 0x00ff0000) /* Auto responder BBP register 3 data. */
606 #define ARCSR1_AR_BBP_ID3 \
607  FIELD32(24, 0xff000000) /* Auto responder BBP register 3 Id. */
608 
609 /*
610  * Miscellaneous Registers.
611  * Some values are set in TU, whereas 1 TU == 1024 us.
612  */
613 
614 /*
615  * PCISR: PCI control register.
616  */
617 #define PCICSR_BIG_ENDIAN \
618  FIELD32(0, 0x00000001) /* 1: big endian, 0: little endian. */
619 #define PCICSR_RX_TRESHOLD \
620  FIELD32(1, 0x00000006) /* rx threshold in dw to start pci access */
621 /* 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. */
622 #define PCICSR_TX_TRESHOLD \
623  FIELD32(3, 0x00000018) /* tx threshold in dw to start pci access */
624 /* 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. */
625 #define PCICSR_BURST_LENTH FIELD32(5, 0x00000060) /* pci burst length */
626 /* 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. */
627 #define PCICSR_ENABLE_CLK FIELD32(7, 0x00000080) /* enable clk_run, */
628 /* pci clock can't going down to non-operational. */
629 #define PCICSR_READ_MULTIPLE \
630  FIELD32(8, 0x00000100) /* Enable memory read multiple. */
631 #define PCICSR_WRITE_INVALID \
632  FIELD32(9, 0x00000200) /* Enable memory write & invalid. */
633 
634 /*
635  * PWRCSR1: Manual power control / status register.
636  * state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
637  */
638 #define PWRCSR1_SET_STATE \
639  FIELD32(0, \
640  0x00000001) /* set state. Write 1 to trigger, self cleared. */
641 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(1, 0x00000006) /* BBP desired state. */
642 #define PWRCSR1_RF_DESIRE_STATE FIELD32(3, 0x00000018) /* RF desired state. */
643 #define PWRCSR1_BBP_CURR_STATE FIELD32(5, 0x00000060) /* BBP current state. */
644 #define PWRCSR1_RF_CURR_STATE FIELD32(7, 0x00000180) /* RF current state. */
645 #define PWRCSR1_PUT_TO_SLEEP \
646  FIELD32(9, \
647  0x00000200) /* put to sleep. Write 1 to trigger, self cleared. */
648 
649 /*
650  * TIMECSR: Timer control register.
651  */
652 #define TIMECSR_US_COUNT \
653  FIELD32(0, 0x000000ff) /* 1 us timer count in units of clock cycles. */
654 #define TIMECSR_US_64_COUNT \
655  FIELD32(8, 0x0000ff00) /* 64 us timer count in units of 1 us timer. */
656 #define TIMECSR_BEACON_EXPECT \
657  FIELD32(16, 0x00070000) /* Beacon expect window. */
658 
659 /*
660  * MACCSR1: MAC configuration register 1.
661  */
662 #define MACCSR1_KICK_RX \
663  FIELD32(0, 0x00000001) /* kick one-shot rx in one-shot rx mode. */
664 #define MACCSR1_ONESHOT_RXMODE \
665  FIELD32(1, 0x00000002) /* enable one-shot rx mode for debugging. */
666 #define MACCSR1_BBPRX_RESET_MODE \
667  FIELD32(2, 0x00000004) /* ralink bbp rx reset mode. */
668 #define MACCSR1_AUTO_TXBBP \
669  FIELD32(3, 0x00000008) /* auto tx logic access bbp control register. */
670 #define MACCSR1_AUTO_RXBBP \
671  FIELD32(4, 0x00000010) /* auto rx logic access bbp control register. */
672 #define MACCSR1_LOOPBACK FIELD32(5, 0x00000060) /* loopback mode. */
673 /* 0: normal, 1: internal, 2: external, 3:rsvd. */
674 #define MACCSR1_INTERSIL_IF \
675  FIELD32(7, 0x00000080) /* intersil if calibration pin. */
676 
677 /*
678  * RALINKCSR: Ralink Rx auto-reset BBCR.
679  */
680 #define RALINKCSR_AR_BBP_DATA0 \
681  FIELD32(0, 0x000000ff) /* auto reset bbp register 0 data. */
682 #define RALINKCSR_AR_BBP_ID0 \
683  FIELD32(8, 0x00007f00) /* auto reset bbp register 0 id. */
684 #define RALINKCSR_AR_BBP_VALID0 \
685  FIELD32(15, 0x00008000) /* auto reset bbp register 0 valid. */
686 #define RALINKCSR_AR_BBP_DATA1 \
687  FIELD32(16, 0x00ff0000) /* auto reset bbp register 1 data. */
688 #define RALINKCSR_AR_BBP_ID1 \
689  FIELD32(24, 0x7f000000) /* auto reset bbp register 1 id. */
690 #define RALINKCSR_AR_BBP_VALID1 \
691  FIELD32(31, 0x80000000) /* auto reset bbp register 1 valid. */
692 
693 /*
694  * BCNCSR: Beacon interval control register.
695  */
696 #define BCNCSR_CHANGE \
697  FIELD32(0, 0x00000001) /* write one to change beacon interval. */
698 #define BCNCSR_DELTATIME FIELD32(1, 0x0000001e) /* the delta time value. */
699 #define BCNCSR_NUM_BEACON \
700  FIELD32(5, 0x00001fe0) /* number of beacon according to mode. */
701 #define BCNCSR_MODE FIELD32(13, 0x00006000) /* please refer to asic specs. */
702 #define BCNCSR_PLUS \
703  FIELD32(15, 0x00008000) /* plus or minus delta time value. */
704 
705 /*
706  * BBPCSR: BBP serial control register.
707  */
708 #define BBPCSR_VALUE \
709  FIELD32(0, 0x000000ff) /* register value to program into bbp. */
710 #define BBPCSR_REGNUM FIELD32(8, 0x00007f00) /* selected bbp register. */
711 #define BBPCSR_BUSY \
712  FIELD32(15, 0x00008000) /* 1: asic is busy execute bbp programming. */
713 #define BBPCSR_WRITE_CONTROL \
714  FIELD32(16, 0x00010000) /* 1: write bbp, 0: read bbp. */
715 
716 /*
717  * RFCSR: RF serial control register.
718  */
719 #define RFCSR_VALUE \
720  FIELD32(0, 0x00ffffff) /* register value + id to program into rf/if. */
721 #define RFCSR_NUMBER_OF_BITS \
722  FIELD32(24, \
723  0x1f000000) /* number of bits used in value (i:20, rfmd:22). */
724 #define RFCSR_IF_SELECT \
725  FIELD32(29, 0x20000000) /* chip to program: 0: rf, 1: if. */
726 #define RFCSR_PLL_LD FIELD32(30, 0x40000000) /* rf pll_ld status. */
727 #define RFCSR_BUSY \
728  FIELD32(31, 0x80000000) /* 1: asic is busy execute rf programming. */
729 
730 /*
731  * LEDCSR: LED control register.
732  */
733 #define LEDCSR_ON_PERIOD FIELD32(0, 0x000000ff) /* on period, default 70ms. */
734 #define LEDCSR_OFF_PERIOD FIELD32(8, 0x0000ff00) /* off period, default 30ms. */
735 #define LEDCSR_LINK FIELD32(16, 0x00010000) /* 0: linkoff, 1: linkup. */
736 #define LEDCSR_ACTIVITY FIELD32(17, 0x00020000) /* 0: idle, 1: active. */
737 #define LEDCSR_LINK_POLARITY \
738  FIELD32(18, 0x00040000) /* 0: active low, 1: active high. */
739 #define LEDCSR_ACTIVITY_POLARITY \
740  FIELD32(19, 0x00080000) /* 0: active low, 1: active high. */
741 #define LEDCSR_LED_DEFAULT \
742  FIELD32(20, 0x00100000) /* LED state for "enable" 0: ON, 1: OFF. */
743 
744 /*
745  * GPIOCSR: GPIO control register.
746  */
747 #define GPIOCSR_BIT0 FIELD32(0, 0x00000001)
748 #define GPIOCSR_BIT1 FIELD32(1, 0x00000002)
749 #define GPIOCSR_BIT2 FIELD32(2, 0x00000004)
750 #define GPIOCSR_BIT3 FIELD32(3, 0x00000008)
751 #define GPIOCSR_BIT4 FIELD32(4, 0x00000010)
752 #define GPIOCSR_BIT5 FIELD32(5, 0x00000020)
753 #define GPIOCSR_BIT6 FIELD32(6, 0x00000040)
754 #define GPIOCSR_BIT7 FIELD32(7, 0x00000080)
755 #define GPIOCSR_DIR0 FIELD32(8, 0x00000100)
756 #define GPIOCSR_DIR1 FIELD32(9, 0x00000200)
757 #define GPIOCSR_DIR2 FIELD32(10, 0x00000400)
758 #define GPIOCSR_DIR3 FIELD32(11, 0x00000800)
759 #define GPIOCSR_DIR4 FIELD32(12, 0x00001000)
760 #define GPIOCSR_DIR5 FIELD32(13, 0x00002000)
761 #define GPIOCSR_DIR6 FIELD32(14, 0x00004000)
762 #define GPIOCSR_DIR7 FIELD32(15, 0x00008000)
763 
764 /*
765  * BCNCSR1: Tx BEACON offset time control register.
766  */
767 #define BCNCSR1_PRELOAD \
768  FIELD32(0, 0x0000ffff) /* beacon timer offset in units of usec. */
769 #define BCNCSR1_BEACON_CWMIN FIELD32(16, 0x000f0000) /* 2^CwMin. */
770 
771 /*
772  * MACCSR2: TX_PE to RX_PE turn-around time control register
773  */
774 #define MACCSR2_DELAY \
775  FIELD32(0, \
776  0x000000ff) /* RX_PE low width, in units of pci clock cycle. */
777 
778 /*
779  * SECCSR1_RT2509: WEP control register
780  */
781 #define SECCSR1_KICK_ENCRYPT \
782  FIELD32(0, 0x00000001) /* Kick encryption engine, self-clear. */
783 #define SECCSR1_ONE_SHOT \
784  FIELD32(1, 0x00000002) /* 0: ring mode, 1: One shot only mode. */
785 #define SECCSR1_DESC_ADDRESS \
786  FIELD32(2, 0xfffffffc) /* Descriptor physical address of frame. */
787 
788 /*
789  * RF registers
790  */
791 #define RF1_TUNER FIELD32(17, 0x00020000)
792 #define RF3_TUNER FIELD32(8, 0x00000100)
793 #define RF3_TXPOWER FIELD32(9, 0x00003e00)
794 
795 /*
796  * EEPROM content format.
797  * The wordsize of the EEPROM is 16 bits.
798  */
799 
800 /*
801  * EEPROM operation defines.
802  */
803 #define EEPROM_WIDTH_93c46 6
804 #define EEPROM_WIDTH_93c66 8
805 #define EEPROM_WRITE_OPCODE 0x05
806 #define EEPROM_READ_OPCODE 0x06
807 
808 /*
809  * EEPROM antenna.
810  */
811 #define EEPROM_ANTENNA_NUM FIELD16(0, 0x0003) /* Number of antenna's. */
812 #define EEPROM_ANTENNA_TX_DEFAULT \
813  FIELD16(2, 0x000c) /* Default antenna 0: diversity, 1: A, 2: B. */
814 #define EEPROM_ANTENNA_RX_DEFAULT \
815  FIELD16(4, 0x0030) /* Default antenna 0: diversity, 1: A, 2: B. */
816 #define EEPROM_ANTENNA_LED_MODE \
817  FIELD16(6, 0x01c0) /* 0: default, 1: TX/RX activity, */
818 /* 2: Single LED (ignore link), 3: reserved. */
819 #define EEPROM_ANTENNA_DYN_TXAGC \
820  FIELD16(9, 0x0200) /* Dynamic TX AGC control. */
821 #define EEPROM_ANTENNA_HARDWARE_RADIO \
822  FIELD16(10, 0x0400) /* 1: Hardware controlled radio. Read GPIO0. */
823 #define EEPROM_ANTENNA_RF_TYPE \
824  FIELD16(11, 0xf800) /* rf_type of this adapter. */
825 
826 /*
827  * EEPROM geography.
828  */
829 #define EEPROM_GEOGRAPHY_GEO \
830  FIELD16(8, 0x0f00) /* Default geography setting for device. */
831 
832 /*
833  * EEPROM NIC config.
834  */
835 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0, 0x0001) /* 0: enable, 1: disable. */
836 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(1, 0x0002) /* 0: enable, 1: disable. */
837 #define EEPROM_NIC_CCK_TX_POWER \
838  FIELD16(2, 0x000c) /* CCK TX power compensation. */
839 
840 /*
841  * EEPROM TX power.
842  */
843 #define EEPROM_TX_POWER1 FIELD16(0, 0x00ff)
844 #define EEPROM_TX_POWER2 FIELD16(8, 0xff00)
845 
846 /*
847  * EEPROM BBP.
848  */
849 #define EEPROM_BBP_VALUE FIELD16(0, 0x00ff)
850 #define EEPROM_BBP_REG_ID FIELD16(8, 0xff00)
851 
852 /*
853  * EEPROM VERSION.
854  */
855 #define EEPROM_VERSION_FAE FIELD16(0, 0x00ff) /* FAE release number. */
856 #define EEPROM_VERSION FIELD16(8, 0xff00)
857 
858 /*
859  * DMA ring defines and data structures.
860  */
861 
862 /*
863  * Size of a single descriptor.
864  */
865 #define SIZE_DESCRIPTOR 48
866 
867 /*
868  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
869  */
870 struct _txd {
871  u32 word0;
872 #define TXD_W0_OWNER_NIC FIELD32(0, 0x00000001)
873 #define TXD_W0_VALID FIELD32(1, 0x00000002)
874 #define TXD_W0_RESULT FIELD32(2, 0x0000001c) /* Set by device. */
875 #define TXD_W0_RETRY_COUNT FIELD32(5, 0x000000e0) /* Set by device. */
876 #define TXD_W0_MORE_FRAG FIELD32(8, 0x00000100) /* Set by device. */
877 #define TXD_W0_ACK FIELD32(9, 0x00000200)
878 #define TXD_W0_TIMESTAMP FIELD32(10, 0x00000400)
879 #define TXD_W0_OFDM FIELD32(11, 0x00000800)
880 #define TXD_W0_CIPHER_OWNER FIELD32(12, 0x00001000)
881 #define TXD_W0_IFS FIELD32(13, 0x00006000)
882 #define TXD_W0_RETRY_MODE FIELD32(15, 0x00008000)
883 #define TXD_W0_DATABYTE_COUNT FIELD32(16, 0x0fff0000)
884 #define TXD_W0_CIPHER_ALG FIELD32(29, 0xe0000000)
885 
886  u32 word1;
887 #define TXD_W1_BUFFER_ADDRESS FIELD32(0, 0xffffffff)
888 
889  u32 word2;
890 #define TXD_W2_IV_OFFSET FIELD32(0, 0x0000003f)
891 #define TXD_W2_AIFS FIELD32(6, 0x000000c0)
892 #define TXD_W2_CWMIN FIELD32(8, 0x00000f00)
893 #define TXD_W2_CWMAX FIELD32(12, 0x0000f000)
894 
895  u32 word3;
896 #define TXD_W3_PLCP_SIGNAL FIELD32(0, 0x000000ff)
897 #define TXD_W3_PLCP_SERVICE FIELD32(8, 0x0000ff00)
898 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(16, 0x00ff0000)
899 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(24, 0xff000000)
900 
901  u32 word4;
902 #define TXD_W4_IV FIELD32(0, 0xffffffff)
903 
904  u32 word5;
905 #define TXD_W5_EIV FIELD32(0, 0xffffffff)
906 
907  u32 word6;
908 #define TXD_W6_KEY FIELD32(0, 0xffffffff)
909 
910  u32 word7;
911 #define TXD_W7_KEY FIELD32(0, 0xffffffff)
912 
913  u32 word8;
914 #define TXD_W8_KEY FIELD32(0, 0xffffffff)
915 
916  u32 word9;
917 #define TXD_W9_KEY FIELD32(0, 0xffffffff)
918 
919  u32 word10;
920 #define TXD_W10_RTS FIELD32(0, 0x00000001)
921 #define TXD_W10_TX_RATE FIELD32(0, 0x000000fe) /* For module only. */
922 } __attribute__((packed));
923 
924 /*
925  * RX descriptor format for RX Ring.
926  */
927 struct _rxd {
928  u32 word0;
929 #define RXD_W0_OWNER_NIC FIELD32(0, 0x00000001)
930 #define RXD_W0_UNICAST_TO_ME FIELD32(1, 0x00000002)
931 #define RXD_W0_MULTICAST FIELD32(2, 0x00000004)
932 #define RXD_W0_BROADCAST FIELD32(3, 0x00000008)
933 #define RXD_W0_MY_BSS FIELD32(4, 0x00000010)
934 #define RXD_W0_CRC FIELD32(5, 0x00000020)
935 #define RXD_W0_OFDM FIELD32(6, 0x00000040)
936 #define RXD_W0_PHYSICAL_ERROR FIELD32(7, 0x00000080)
937 #define RXD_W0_CIPHER_OWNER FIELD32(8, 0x00000100)
938 #define RXD_W0_ICV_ERROR FIELD32(9, 0x00000200)
939 #define RXD_W0_IV_OFFSET FIELD32(10, 0x0000fc00)
940 #define RXD_W0_DATABYTE_COUNT FIELD32(16, 0x0fff0000)
941 #define RXD_W0_CIPHER_ALG FIELD32(29, 0xe0000000)
942 
943  u32 word1;
944 #define RXD_W1_BUFFER_ADDRESS FIELD32(0, 0xffffffff)
945 
946  u32 word2;
947 #define RXD_W2_BBR0 FIELD32(0, 0x000000ff)
948 #define RXD_W2_RSSI FIELD32(8, 0x0000ff00)
949 #define RXD_W2_TA FIELD32(16, 0xffff0000)
950 
951  u32 word3;
952 #define RXD_W3_TA FIELD32(0, 0xffffffff)
953 
954  u32 word4;
955 #define RXD_W4_IV FIELD32(0, 0xffffffff)
956 
957  u32 word5;
958 #define RXD_W5_EIV FIELD32(0, 0xffffffff)
959 
960  u32 word6;
961 #define RXD_W6_KEY FIELD32(0, 0xffffffff)
962 
963  u32 word7;
964 #define RXD_W7_KEY FIELD32(0, 0xffffffff)
965 
966  u32 word8;
967 #define RXD_W8_KEY FIELD32(0, 0xffffffff)
968 
969  u32 word9;
970 #define RXD_W9_KEY FIELD32(0, 0xffffffff)
971 
972  u32 word10;
973 #define RXD_W10_DROP FIELD32(0, 0x00000001)
974 } __attribute__((packed));
975 
976 /*
977  * _rt2x00_pci
978  * This is the main structure which contains all variables required to communicate with the PCI device.
979  */
980 struct _rt2x00_pci {
981  /*
982  * PCI device structure.
983  */
984  struct pci_dev *pci_dev;
985 
986  /*
987  * Chipset identification.
988  */
989  struct _rt2x00_chip chip;
990 
991  /*
992  * csr_addr
993  * Base address of device registers, all exact register addresses are calculated from this address.
994  */
995  void __iomem *csr_addr;
996 
997  /*
998  * RF register values for current channel.
999  */
1000  struct _rf_channel channel;
1001 
1002  /*
1003  * EEPROM bus width.
1004  */
1005  u8 eeprom_width;
1006 
1007  u8 __pad; /* For alignment only. */
1008 
1009  /*
1010  * EEPROM BBP data.
1011  */
1012  u16 eeprom[EEPROM_BBP_SIZE];
1013 
1014  /*
1015  * DMA packet ring.
1016  */
1017  struct _data_ring rx;
1018  struct _data_ring tx;
1019 
1020  rtdm_irq_t irq_handle;
1021  rtdm_lock_t lock;
1022 
1023 } __attribute__((packed));
1024 
1025 static int rt2x00_get_rf_value(const struct _rt2x00_chip *chip,
1026  const u8 channel, struct _rf_channel *rf_reg)
1027 {
1028  int index = 0x00;
1029 
1030  index = rt2x00_get_channel_index(channel);
1031  if (index < 0)
1032  return -EINVAL;
1033 
1034  memset(rf_reg, 0x00, sizeof(*rf_reg));
1035 
1036  if (rt2x00_rf(chip, RF2522)) {
1037  rf_reg->rf1 = 0x00002050;
1038  rf_reg->rf3 = 0x00000101;
1039  goto update_rf2_1;
1040  }
1041  if (rt2x00_rf(chip, RF2523)) {
1042  rf_reg->rf1 = 0x00022010;
1043  rf_reg->rf3 = 0x000e0111;
1044  rf_reg->rf4 = 0x00000a1b;
1045  goto update_rf2_2;
1046  }
1047  if (rt2x00_rf(chip, RF2524)) {
1048  rf_reg->rf1 = 0x00032020;
1049  rf_reg->rf3 = 0x00000101;
1050  rf_reg->rf4 = 0x00000a1b;
1051  goto update_rf2_2;
1052  }
1053  if (rt2x00_rf(chip, RF2525)) {
1054  rf_reg->rf1 = 0x00022020;
1055  rf_reg->rf2 = 0x00080000;
1056  rf_reg->rf3 = 0x00060111;
1057  rf_reg->rf4 = 0x00000a1b;
1058  goto update_rf2_2;
1059  }
1060  if (rt2x00_rf(chip, RF2525E)) {
1061  rf_reg->rf2 = 0x00080000;
1062  rf_reg->rf3 = 0x00060111;
1063  goto update_rf2_3;
1064  }
1065  if (rt2x00_rf(chip, RF5222)) {
1066  rf_reg->rf3 = 0x00000101;
1067  goto update_rf2_3;
1068  }
1069 
1070  return -EINVAL;
1071 
1072 update_rf2_1: /* RF2522. */
1073  rf_reg->rf2 = 0x000c1fda + (index * 0x14);
1074  if (channel == 14)
1075  rf_reg->rf2 += 0x0000001c;
1076  goto exit;
1077 
1078 update_rf2_2: /* RF2523, RF2524, RF2525. */
1079  rf_reg->rf2 |= 0x00000c9e + (index * 0x04);
1080  if (rf_reg->rf2 & 0x00000040)
1081  rf_reg->rf2 += 0x00000040;
1082  if (channel == 14) {
1083  rf_reg->rf2 += 0x08;
1084  rf_reg->rf4 &= ~0x00000018;
1085  }
1086  goto exit;
1087 
1088 update_rf2_3: /* RF2525E, RF5222. */
1089  if (OFDM_CHANNEL(channel)) {
1090  rf_reg->rf1 = 0x00022020;
1091  rf_reg->rf2 |= 0x00001136 + (index * 0x04);
1092  if (rf_reg->rf2 & 0x00000040)
1093  rf_reg->rf2 += 0x00000040;
1094  if (channel == 14) {
1095  rf_reg->rf2 += 0x04;
1096  rf_reg->rf4 = 0x00000a1b;
1097  } else {
1098  rf_reg->rf4 = 0x00000a0b;
1099  }
1100  } else if (UNII_LOW_CHANNEL(channel)) {
1101  rf_reg->rf1 = 0x00022010;
1102  rf_reg->rf2 = 0x00018896 + (index * 0x04);
1103  rf_reg->rf4 = 0x00000a1f;
1104  } else if (HIPERLAN2_CHANNEL(channel)) {
1105  rf_reg->rf1 = 0x00022010;
1106  rf_reg->rf2 = 0x00008802 + (index * 0x04);
1107  rf_reg->rf4 = 0x00000a0f;
1108  } else if (UNII_HIGH_CHANNEL(channel)) {
1109  rf_reg->rf1 = 0x00022020;
1110  rf_reg->rf2 = 0x000090a6 + (index * 0x08);
1111  rf_reg->rf4 = 0x00000a07;
1112  }
1113 
1114 exit:
1115  rf_reg->rf1 = cpu_to_le32(rf_reg->rf1);
1116  rf_reg->rf2 = cpu_to_le32(rf_reg->rf2);
1117  rf_reg->rf3 = cpu_to_le32(rf_reg->rf3);
1118  rf_reg->rf4 = cpu_to_le32(rf_reg->rf4);
1119 
1120  return 0;
1121 }
1122 
1123 /*
1124  * Get txpower value in dBm mathing the requested percentage.
1125  */
1126 static inline u8 rt2x00_get_txpower(const struct _rt2x00_chip *chip,
1127  const u8 tx_power)
1128 {
1129  return tx_power / 100 * 31;
1130 
1131  /*
1132  if(tx_power <= 3)
1133  return 19;
1134  else if(tx_power <= 12)
1135  return 22;
1136  else if(tx_power <= 25)
1137  return 25;
1138  else if(tx_power <= 50)
1139  return 28;
1140  else if(tx_power <= 75)
1141  return 30;
1142  else if(tx_power <= 100)
1143  return 31;
1144 
1145  ERROR("Invalid tx_power.\n");
1146  return 31;
1147  */
1148 }
1149 
1150 /*
1151  * Ring handlers.
1152  */
1153 static inline int
1154 rt2x00_pci_alloc_ring(struct _rt2x00_core *core, struct _data_ring *ring,
1155  const u8 ring_type, const u16 max_entries,
1156  const u16 entry_size, const u16 desc_size)
1157 {
1158  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1159 
1160  rt2x00_init_ring(core, ring, ring_type, max_entries, entry_size,
1161  desc_size);
1162 
1163  ring->data_addr =
1164  dma_alloc_coherent(&rt2x00pci->pci_dev->dev, ring->mem_size,
1165  &ring->data_dma, GFP_KERNEL);
1166  if (!ring->data_addr)
1167  return -ENOMEM;
1168 
1169  memset(ring->data_addr, 0x00, ring->mem_size);
1170 
1171  return 0;
1172 }
1173 
1174 static int rt2x00_pci_alloc_rings(struct _rt2x00_core *core)
1175 {
1176  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1177 
1178  if (rt2x00_pci_alloc_ring(core, &rt2x00pci->rx, RING_RX, RX_ENTRIES,
1179  DATA_FRAME_SIZE, SIZE_DESCRIPTOR) ||
1180  rt2x00_pci_alloc_ring(core, &rt2x00pci->tx, RING_TX, TX_ENTRIES,
1181  DATA_FRAME_SIZE, SIZE_DESCRIPTOR)) {
1182  ERROR("DMA allocation failed.\n");
1183  return -ENOMEM;
1184  }
1185 
1186  return 0;
1187 }
1188 
1189 static inline void rt2x00_pci_free_ring(struct _data_ring *ring)
1190 {
1191  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(ring->core);
1192 
1193  if (ring->data_addr)
1194  dma_free_coherent(&rt2x00pci->pci_dev->dev, ring->mem_size,
1195  ring->data_addr, ring->data_dma);
1196  ring->data_addr = NULL;
1197 
1198  rt2x00_deinit_ring(ring);
1199 }
1200 
1201 static void rt2x00_pci_free_rings(struct _rt2x00_core *core)
1202 {
1203  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1204 
1205  rt2x00_pci_free_ring(&rt2x00pci->rx);
1206  rt2x00_pci_free_ring(&rt2x00pci->tx);
1207 }
1208 
1209 /*
1210  * Macro's for calculating exact position in data ring.
1211  */
1212 #define DESC_BASE(__ring) ((void *)((__ring)->data_addr))
1213 #define DATA_BASE(__ring) \
1214  ((void *)(DESC_BASE(__ring) + \
1215  ((__ring)->max_entries * (__ring)->desc_size)))
1216 
1217 #define __DESC_ADDR(__ring, __index) \
1218  ((void *)(DESC_BASE(__ring) + ((__index) * (__ring)->desc_size)))
1219 #define __DATA_ADDR(__ring, __index) \
1220  ((void *)(DATA_BASE(__ring) + ((__index) * (__ring)->entry_size)))
1221 
1222 #define DESC_ADDR(__ring) (__DESC_ADDR(__ring, (__ring)->index))
1223 #define DESC_ADDR_DONE(__ring) (__DESC_ADDR(__ring, (__ring)->index_done))
1224 
1225 #define DATA_ADDR(__ring) (__DATA_ADDR(__ring, (__ring)->index))
1226 #define DATA_ADDR_DONE(__ring) (__DATA_ADDR(__ring, (__ring)->index_done))
1227 
1228 /*
1229  * Register access.
1230  * All access to the registers will go through rt2x00_register_read and rt2x00_register_write.
1231  * BBP and RF register require indirect register access through the register BBPCSR and RFCSR.
1232  * The indirect register access work with busy bits, and a read or write function call can fail.
1233  * Specific fields within a register can be accessed using the set and get field routines,
1234  * these function will handle the requirement of little_endian and big_endian conversions.
1235  */
1236 #define REGISTER_BUSY_COUNT \
1237  10 /* Number of retries before failing access BBP & RF indirect register */
1238 #define REGISTER_BUSY_DELAY \
1239  100 /* Delay between each register access retry. (us) */
1240 
1241 static void rt2x00_register_read(const struct _rt2x00_pci *rt2x00pci,
1242  const unsigned long offset, u32 *value)
1243 {
1244  *value = readl((void *)(rt2x00pci->csr_addr + offset));
1245 }
1246 
1247 static void rt2x00_register_multiread(const struct _rt2x00_pci *rt2x00pci,
1248  const unsigned long offset, u32 *value,
1249  const u16 length)
1250 {
1251  memcpy_fromio((void *)value, (void *)(rt2x00pci->csr_addr + offset),
1252  length);
1253 }
1254 
1255 static void rt2x00_register_write(const struct _rt2x00_pci *rt2x00pci,
1256  const unsigned long offset, const u32 value)
1257 {
1258  writel(value, (void *)(rt2x00pci->csr_addr + offset));
1259 }
1260 
1261 static void rt2x00_register_multiwrite(const struct _rt2x00_pci *rt2x00pci,
1262  const unsigned long offset, u32 *value,
1263  const u16 length)
1264 {
1265  memcpy_toio((void *)(rt2x00pci->csr_addr + offset), (void *)value,
1266  length);
1267 }
1268 
1269 static void rt2x00_bbp_regwrite(const struct _rt2x00_pci *rt2x00pci,
1270  const u8 reg_id, const u8 value)
1271 {
1272  u32 reg = 0x00000000;
1273  u8 counter = 0x00;
1274 
1275  for (counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++) {
1276  rt2x00_register_read(rt2x00pci, BBPCSR, &reg);
1277  if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
1278  goto bbp_write;
1279  udelay(REGISTER_BUSY_DELAY);
1280  }
1281 
1282  ERROR("BBPCSR register busy. Write failed\n");
1283  return;
1284 
1285 bbp_write:
1286  reg = 0x00000000;
1287  rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
1288  rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
1289  rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
1290  rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
1291 
1292  rt2x00_register_write(rt2x00pci, BBPCSR, reg);
1293 }
1294 
1295 static void rt2x00_bbp_regread(const struct _rt2x00_pci *rt2x00pci,
1296  const u8 reg_id, u8 *value)
1297 {
1298  u32 reg = 0x00000000;
1299  u8 counter = 0x00;
1300 
1301  /*
1302  * We first have to acquire the requested BBP register,
1303  * so we write the register id into the BBP register first.
1304  */
1305  rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
1306  rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
1307  rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
1308 
1309  rt2x00_register_write(rt2x00pci, BBPCSR, reg);
1310 
1311  for (counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++) {
1312  rt2x00_register_read(rt2x00pci, BBPCSR, &reg);
1313  if (!rt2x00_get_field32(reg, BBPCSR_BUSY)) {
1314  *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
1315  return;
1316  }
1317  udelay(REGISTER_BUSY_DELAY);
1318  }
1319 
1320  ERROR("BBPCSR register busy. Read failed\n");
1321  *value = 0xff;
1322 }
1323 
1324 static void rt2x00_rf_regwrite(const struct _rt2x00_pci *rt2x00pci,
1325  const u32 value)
1326 {
1327  u32 reg = 0x00000000;
1328  u8 counter = 0x00;
1329 
1330  for (counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++) {
1331  rt2x00_register_read(rt2x00pci, RFCSR, &reg);
1332  if (!rt2x00_get_field32(reg, RFCSR_BUSY))
1333  goto rf_write;
1334  udelay(REGISTER_BUSY_DELAY);
1335  }
1336 
1337  ERROR("RFCSR register busy. Write failed\n");
1338  return;
1339 
1340 rf_write:
1341  reg = value;
1342  rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
1343  rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
1344  rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
1345 
1346  // printk(KERN_INFO "DEBUG: %s:%d: reg=%x\n", __FILE__, __LINE__, reg);
1347 
1348  rt2x00_register_write(rt2x00pci, RFCSR, reg);
1349 }
1350 
1351 /*
1352  * EEPROM access.
1353  * The EEPROM is being accessed by word index.
1354  * rt2x00_eeprom_read_word is the main access function that can be called by
1355  * the rest of the module. It will take the index number of the eeprom word
1356  * and the bus width.
1357  */
1358 static inline void rt2x00_eeprom_pulse_high(const struct _rt2x00_pci *rt2x00pci,
1359  u32 *flags)
1360 {
1361  rt2x00_set_field32(flags, CSR21_EEPROM_DATA_CLOCK, 1);
1362  rt2x00_register_write(rt2x00pci, CSR21, *flags);
1363  udelay(1);
1364 }
1365 
1366 static inline void rt2x00_eeprom_pulse_low(const struct _rt2x00_pci *rt2x00pci,
1367  u32 *flags)
1368 {
1369  rt2x00_set_field32(flags, CSR21_EEPROM_DATA_CLOCK, 0);
1370  rt2x00_register_write(rt2x00pci, CSR21, *flags);
1371  udelay(1);
1372 }
1373 
1374 static void rt2x00_eeprom_shift_out_bits(const struct _rt2x00_pci *rt2x00pci,
1375  const u16 data, const u16 count)
1376 {
1377  u32 flags = 0x00000000;
1378  u32 mask = 0x0001 << (count - 1);
1379 
1380  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1381 
1382  /*
1383  * Clear data flags.
1384  */
1385  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1386  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1387 
1388  /*
1389  * Start writing all bits.
1390  */
1391  do {
1392  /*
1393  * Only set the data_in flag when we are at the correct bit.
1394  */
1395  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN,
1396  (data & mask) ? 1 : 0);
1397 
1398  rt2x00_register_write(rt2x00pci, CSR21, flags);
1399 
1400  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1401  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1402 
1403  /*
1404  * Shift to next bit.
1405  */
1406  mask >>= 1;
1407  } while (mask);
1408 
1409  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1410  rt2x00_register_write(rt2x00pci, CSR21, flags);
1411 }
1412 
1413 static void rt2x00_eeprom_shift_in_bits(const struct _rt2x00_pci *rt2x00pci,
1414  u16 *data)
1415 {
1416  u32 flags = 0x00000000;
1417  u8 counter = 0x00;
1418 
1419  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1420 
1421  /*
1422  * Clear data flags.
1423  */
1424  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1425  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1426 
1427  /*
1428  * Start reading all 16 bits.
1429  */
1430  for (counter = 0; counter < 16; counter++) {
1431  /*
1432  * Shift to the next bit.
1433  */
1434  *data <<= 1;
1435 
1436  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1437 
1438  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1439 
1440  /*
1441  * Clear data_in flag and set the data bit to 1 when the data_out flag is set.
1442  */
1443  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1444  if (rt2x00_get_field32(flags, CSR21_EEPROM_DATA_OUT))
1445  *data |= 1;
1446 
1447  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1448  }
1449 }
1450 
1451 static u16 rt2x00_eeprom_read_word(const struct _rt2x00_pci *rt2x00pci,
1452  const u8 word)
1453 {
1454  u32 flags = 0x00000000;
1455  u16 data = 0x0000;
1456 
1457  /*
1458  * Clear all flags, and enable chip select.
1459  */
1460  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1461  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1462  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1463  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_CLOCK, 0);
1464  rt2x00_set_field32(&flags, CSR21_EEPROM_CHIP_SELECT, 1);
1465  rt2x00_register_write(rt2x00pci, CSR21, flags);
1466 
1467  /*
1468  * kick a pulse.
1469  */
1470  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1471  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1472 
1473  /*
1474  * Select the read opcode and bus_width.
1475  */
1476  rt2x00_eeprom_shift_out_bits(rt2x00pci, EEPROM_READ_OPCODE, 3);
1477  rt2x00_eeprom_shift_out_bits(rt2x00pci, word, rt2x00pci->eeprom_width);
1478 
1479  rt2x00_eeprom_shift_in_bits(rt2x00pci, &data);
1480 
1481  /*
1482  * Clear chip_select and data_in flags.
1483  */
1484  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1485  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1486  rt2x00_set_field32(&flags, CSR21_EEPROM_CHIP_SELECT, 0);
1487  rt2x00_register_write(rt2x00pci, CSR21, flags);
1488 
1489  /*
1490  * kick a pulse.
1491  */
1492  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1493  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1494 
1495  return data;
1496 }
1497 
1498 #endif /* RT2500PCI_H */
rtdm_lock_t
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:551
__attribute__
static int __attribute__((cold))
Test if a mutex structure contains a valid autoinitializer.
Definition: mutex.c:177