Xenomai 3.3.2
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rtcan_c_can.h
1/*
2 * CAN bus driver for Bosch C_CAN controller, ported to Xenomai RTDM
3 *
4 * Copyright 2021, Dario Binacchi <dariobin@libero.it>
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Bhupesh Sharma <bhupesh.sharma@st.com>
8 *
9 * Stephen J. Battazzo <stephen.j.battazzo@nasa.gov>,
10 * MEI Services/NASA Ames Research Center
11 *
12 * Borrowed original driver from:
13 *
14 * Bhupesh Sharma <bhupesh.sharma@st.com>, ST Microelectronics
15 * Borrowed heavily from the C_CAN driver originally written by:
16 * Copyright (C) 2007
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
18 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
19 *
20 * TX and RX NAPI implementation has been removed and replaced with RT Socket CAN implementation.
21 * RT Socket CAN implementation inspired by Flexcan RTDM port by Wolfgang Grandegger <wg@denx.de>
22 *
23 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
24 * Bosch C_CAN user manual can be obtained from:
25 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
26 * users_manual_c_can.pdf
27 *
28 * This file is licensed under the terms of the GNU General Public
29 * License version 2. This program is licensed "as is" without any
30 * warranty of any kind, whether express or implied.
31 */
32
33#ifndef RTCAN_C_CAN_H
34#define RTCAN_C_CAN_H
35
36enum reg {
37 C_CAN_CTRL_REG = 0,
38 C_CAN_CTRL_EX_REG,
39 C_CAN_STS_REG,
40 C_CAN_ERR_CNT_REG,
41 C_CAN_BTR_REG,
42 C_CAN_INT_REG,
43 C_CAN_TEST_REG,
44 C_CAN_BRPEXT_REG,
45 C_CAN_IF1_COMREQ_REG,
46 C_CAN_IF1_COMMSK_REG,
47 C_CAN_IF1_MASK1_REG,
48 C_CAN_IF1_MASK2_REG,
49 C_CAN_IF1_ARB1_REG,
50 C_CAN_IF1_ARB2_REG,
51 C_CAN_IF1_MSGCTRL_REG,
52 C_CAN_IF1_DATA1_REG,
53 C_CAN_IF1_DATA2_REG,
54 C_CAN_IF1_DATA3_REG,
55 C_CAN_IF1_DATA4_REG,
56 C_CAN_IF2_COMREQ_REG,
57 C_CAN_IF2_COMMSK_REG,
58 C_CAN_IF2_MASK1_REG,
59 C_CAN_IF2_MASK2_REG,
60 C_CAN_IF2_ARB1_REG,
61 C_CAN_IF2_ARB2_REG,
62 C_CAN_IF2_MSGCTRL_REG,
63 C_CAN_IF2_DATA1_REG,
64 C_CAN_IF2_DATA2_REG,
65 C_CAN_IF2_DATA3_REG,
66 C_CAN_IF2_DATA4_REG,
67 C_CAN_TXRQST1_REG,
68 C_CAN_TXRQST2_REG,
69 C_CAN_TXRQST3_REG,
70 C_CAN_TXRQST4_REG,
71 C_CAN_NEWDAT1_REG,
72 C_CAN_NEWDAT2_REG,
73 C_CAN_INTPND1_REG,
74 C_CAN_INTPND2_REG,
75 C_CAN_INTPND3_REG,
76 C_CAN_MSGVAL1_REG,
77 C_CAN_MSGVAL2_REG,
78 C_CAN_FUNCTION_REG,
79};
80
81static const u16 reg_map_c_can[] = {
82 [C_CAN_CTRL_REG] = 0x00,
83 [C_CAN_STS_REG] = 0x02,
84 [C_CAN_ERR_CNT_REG] = 0x04,
85 [C_CAN_BTR_REG] = 0x06,
86 [C_CAN_INT_REG] = 0x08,
87 [C_CAN_TEST_REG] = 0x0A,
88 [C_CAN_BRPEXT_REG] = 0x0C,
89 [C_CAN_IF1_COMREQ_REG] = 0x10,
90 [C_CAN_IF1_COMMSK_REG] = 0x12,
91 [C_CAN_IF1_MASK1_REG] = 0x14,
92 [C_CAN_IF1_MASK2_REG] = 0x16,
93 [C_CAN_IF1_ARB1_REG] = 0x18,
94 [C_CAN_IF1_ARB2_REG] = 0x1A,
95 [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
96 [C_CAN_IF1_DATA1_REG] = 0x1E,
97 [C_CAN_IF1_DATA2_REG] = 0x20,
98 [C_CAN_IF1_DATA3_REG] = 0x22,
99 [C_CAN_IF1_DATA4_REG] = 0x24,
100 [C_CAN_IF2_COMREQ_REG] = 0x40,
101 [C_CAN_IF2_COMMSK_REG] = 0x42,
102 [C_CAN_IF2_MASK1_REG] = 0x44,
103 [C_CAN_IF2_MASK2_REG] = 0x46,
104 [C_CAN_IF2_ARB1_REG] = 0x48,
105 [C_CAN_IF2_ARB2_REG] = 0x4A,
106 [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
107 [C_CAN_IF2_DATA1_REG] = 0x4E,
108 [C_CAN_IF2_DATA2_REG] = 0x50,
109 [C_CAN_IF2_DATA3_REG] = 0x52,
110 [C_CAN_IF2_DATA4_REG] = 0x54,
111 [C_CAN_TXRQST1_REG] = 0x80,
112 [C_CAN_TXRQST2_REG] = 0x82,
113 [C_CAN_NEWDAT1_REG] = 0x90,
114 [C_CAN_NEWDAT2_REG] = 0x92,
115 [C_CAN_INTPND1_REG] = 0xA0,
116 [C_CAN_INTPND2_REG] = 0xA2,
117 [C_CAN_MSGVAL1_REG] = 0xB0,
118 [C_CAN_MSGVAL2_REG] = 0xB2,
119};
120
121static const u16 reg_map_d_can[] = {
122 [C_CAN_CTRL_REG] = 0x00,
123 [C_CAN_CTRL_EX_REG] = 0x02,
124 [C_CAN_STS_REG] = 0x04,
125 [C_CAN_ERR_CNT_REG] = 0x08,
126 [C_CAN_BTR_REG] = 0x0C,
127 [C_CAN_BRPEXT_REG] = 0x0E,
128 [C_CAN_INT_REG] = 0x10,
129 [C_CAN_TEST_REG] = 0x14,
130 [C_CAN_FUNCTION_REG] = 0x18,
131 [C_CAN_TXRQST1_REG] = 0x88,
132 [C_CAN_TXRQST2_REG] = 0x8A,
133 [C_CAN_TXRQST3_REG] = 0x8C,
134 [C_CAN_TXRQST4_REG] = 0x8E,
135 [C_CAN_NEWDAT1_REG] = 0x9C,
136 [C_CAN_NEWDAT2_REG] = 0x9E,
137 [C_CAN_INTPND1_REG] = 0xB0,
138 [C_CAN_INTPND2_REG] = 0xB2,
139 [C_CAN_INTPND3_REG] = 0xB4,
140 [C_CAN_MSGVAL1_REG] = 0xC4,
141 [C_CAN_MSGVAL2_REG] = 0xC6,
142 [C_CAN_IF1_COMREQ_REG] = 0x100,
143 [C_CAN_IF1_COMMSK_REG] = 0x102,
144 [C_CAN_IF1_MASK1_REG] = 0x104,
145 [C_CAN_IF1_MASK2_REG] = 0x106,
146 [C_CAN_IF1_ARB1_REG] = 0x108,
147 [C_CAN_IF1_ARB2_REG] = 0x10A,
148 [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
149 [C_CAN_IF1_DATA1_REG] = 0x110,
150 [C_CAN_IF1_DATA2_REG] = 0x112,
151 [C_CAN_IF1_DATA3_REG] = 0x114,
152 [C_CAN_IF1_DATA4_REG] = 0x116,
153 [C_CAN_IF2_COMREQ_REG] = 0x120,
154 [C_CAN_IF2_COMMSK_REG] = 0x122,
155 [C_CAN_IF2_MASK1_REG] = 0x124,
156 [C_CAN_IF2_MASK2_REG] = 0x126,
157 [C_CAN_IF2_ARB1_REG] = 0x128,
158 [C_CAN_IF2_ARB2_REG] = 0x12A,
159 [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
160 [C_CAN_IF2_DATA1_REG] = 0x130,
161 [C_CAN_IF2_DATA2_REG] = 0x132,
162 [C_CAN_IF2_DATA3_REG] = 0x134,
163 [C_CAN_IF2_DATA4_REG] = 0x136,
164};
165
166enum c_can_dev_id {
167 BOSCH_C_CAN_PLATFORM,
168 BOSCH_C_CAN,
169 BOSCH_D_CAN,
170};
171
172struct raminit_bits {
173 u8 start;
174 u8 done;
175};
176
177struct c_can_driver_data {
178 enum c_can_dev_id id;
179
180 int msg_obj_num;
181
182 /* RAMINIT register description. Optional. */
183 const struct raminit_bits *raminit_bits; /* Array of START/DONE bit positions */
184 u8 raminit_num; /* Number of CAN instances on the SoC */
185 bool raminit_pulse; /* If set, sets and clears START bit (pulse) */
186};
187
188/* Out of band RAMINIT register access via syscon regmap */
189struct c_can_raminit {
190 struct regmap *syscon; /* for raminit ctrl. reg. access */
191 unsigned int reg; /* register index within syscon */
192 struct raminit_bits bits;
193 bool needs_pulse;
194};
195
196#define DEV_NAME "rtcan%d"
197#define DRV_NAME "c_can"
198
199/* c_can private data structure */
200struct c_can_priv {
201 struct rtcan_device *dev;
202
203 int irq;
204
205 struct device *device;
206
207 struct can_bittime bit_time;
208 char bus_err_on;
209 int tx_object;
210 int current_status;
211 int last_status;
212 u16 (*read_reg)(const struct c_can_priv *priv, enum reg index);
213 void (*write_reg)(const struct c_can_priv *priv, enum reg index,
214 u16 val);
215 u32 (*read_reg32)(const struct c_can_priv *priv, enum reg index);
216 void (*write_reg32)(const struct c_can_priv *priv, enum reg index,
217 u32 val);
218 void __iomem *base;
219 const u16 *regs;
220 unsigned long irq_flags; /* for request_irq() */
221 atomic_t tx_active;
222 atomic_t tx_cached;
223 rtdm_lock_t tx_cached_lock;
224 unsigned long tx_dir;
225 void *priv; /* for board-specific data */
226 u16 irqstatus;
227 enum c_can_dev_id type;
228 int msg_obj_num;
229 int msg_obj_rx_num;
230 int msg_obj_tx_num;
231 int msg_obj_rx_first;
232 int msg_obj_rx_last;
233 int msg_obj_rx_low_last;
234 u32 msg_obj_rx_mask;
235 u32 rxmasked;
236 int msg_obj_tx_first;
237 int msg_obj_tx_last;
238 int msg_obj_tx_next_mask;
239 u32 comm_rcv_high;
240 u32 *dlc;
241 struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */
242 u32 __iomem *raminit_ctrlreg;
243 unsigned int instance;
244 void (*raminit)(const struct c_can_priv *priv, bool enable);
245};
246
247struct rtcan_device *rtcan_c_can_dev_alloc(int msg_obj_num);
248void rtcan_c_can_dev_free(struct rtcan_device *dev);
249
250int rtcan_c_can_register(struct rtcan_device *dev);
251void rtcan_c_can_unregister(struct rtcan_device *dev);
252
253void rtcan_c_can_set_ethtool_ops(struct rtcan_device *dev);
254
255#endif
rtdm_lock_t
pipeline_spinlock_t rtdm_lock_t
Lock variable.
Definition driver.h:552
atomic_t
Copyright © 2011 Gilles Chanteperdrix gilles.chanteperdrix@xenomai.org.
Definition atomic.h:24
can_bittime
Custom CAN bit-time definition.
Definition can.h:151