Xenomai 3.3.2
Loading...
Searching...
No Matches
ni_tio.h
1/*
2 * Hardware driver for NI general purpose counter
3 * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
4 *
5 * This code is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published
7 * by the Free Software Foundation; either version 2 of the License,
8 * or (at your option) any later version.
9 *
10 * This code is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with Xenomai; if not, write to the Free Software Foundation,
17 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19#ifndef __ANALOGY_NI_TIO_H__
20#define __ANALOGY_NI_TIO_H__
21
22#include <rtdm/analogy/device.h>
23
24#ifdef CONFIG_PCI
25#include "mite.h"
26#endif
27
28enum ni_gpct_register {
29 NITIO_G0_Autoincrement_Reg,
30 NITIO_G1_Autoincrement_Reg,
31 NITIO_G2_Autoincrement_Reg,
32 NITIO_G3_Autoincrement_Reg,
33 NITIO_G0_Command_Reg,
34 NITIO_G1_Command_Reg,
35 NITIO_G2_Command_Reg,
36 NITIO_G3_Command_Reg,
37 NITIO_G0_HW_Save_Reg,
38 NITIO_G1_HW_Save_Reg,
39 NITIO_G2_HW_Save_Reg,
40 NITIO_G3_HW_Save_Reg,
41 NITIO_G0_SW_Save_Reg,
42 NITIO_G1_SW_Save_Reg,
43 NITIO_G2_SW_Save_Reg,
44 NITIO_G3_SW_Save_Reg,
45 NITIO_G0_Mode_Reg,
46 NITIO_G1_Mode_Reg,
47 NITIO_G2_Mode_Reg,
48 NITIO_G3_Mode_Reg,
49 NITIO_G0_LoadA_Reg,
50 NITIO_G1_LoadA_Reg,
51 NITIO_G2_LoadA_Reg,
52 NITIO_G3_LoadA_Reg,
53 NITIO_G0_LoadB_Reg,
54 NITIO_G1_LoadB_Reg,
55 NITIO_G2_LoadB_Reg,
56 NITIO_G3_LoadB_Reg,
57 NITIO_G0_Input_Select_Reg,
58 NITIO_G1_Input_Select_Reg,
59 NITIO_G2_Input_Select_Reg,
60 NITIO_G3_Input_Select_Reg,
61 NITIO_G0_Counting_Mode_Reg,
62 NITIO_G1_Counting_Mode_Reg,
63 NITIO_G2_Counting_Mode_Reg,
64 NITIO_G3_Counting_Mode_Reg,
65 NITIO_G0_Second_Gate_Reg,
66 NITIO_G1_Second_Gate_Reg,
67 NITIO_G2_Second_Gate_Reg,
68 NITIO_G3_Second_Gate_Reg,
69 NITIO_G01_Status_Reg,
70 NITIO_G23_Status_Reg,
71 NITIO_G01_Joint_Reset_Reg,
72 NITIO_G23_Joint_Reset_Reg,
73 NITIO_G01_Joint_Status1_Reg,
74 NITIO_G23_Joint_Status1_Reg,
75 NITIO_G01_Joint_Status2_Reg,
76 NITIO_G23_Joint_Status2_Reg,
77 NITIO_G0_DMA_Config_Reg,
78 NITIO_G1_DMA_Config_Reg,
79 NITIO_G2_DMA_Config_Reg,
80 NITIO_G3_DMA_Config_Reg,
81 NITIO_G0_DMA_Status_Reg,
82 NITIO_G1_DMA_Status_Reg,
83 NITIO_G2_DMA_Status_Reg,
84 NITIO_G3_DMA_Status_Reg,
85 NITIO_G0_ABZ_Reg,
86 NITIO_G1_ABZ_Reg,
87 NITIO_G0_Interrupt_Acknowledge_Reg,
88 NITIO_G1_Interrupt_Acknowledge_Reg,
89 NITIO_G2_Interrupt_Acknowledge_Reg,
90 NITIO_G3_Interrupt_Acknowledge_Reg,
91 NITIO_G0_Status_Reg,
92 NITIO_G1_Status_Reg,
93 NITIO_G2_Status_Reg,
94 NITIO_G3_Status_Reg,
95 NITIO_G0_Interrupt_Enable_Reg,
96 NITIO_G1_Interrupt_Enable_Reg,
97 NITIO_G2_Interrupt_Enable_Reg,
98 NITIO_G3_Interrupt_Enable_Reg,
99 NITIO_Num_Registers,
100};
101
102static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
103 counter_index)
104{
105 switch (counter_index) {
106 case 0:
107 return NITIO_G0_Autoincrement_Reg;
108 break;
109 case 1:
110 return NITIO_G1_Autoincrement_Reg;
111 break;
112 case 2:
113 return NITIO_G2_Autoincrement_Reg;
114 break;
115 case 3:
116 return NITIO_G3_Autoincrement_Reg;
117 break;
118 default:
119 BUG();
120 break;
121 }
122 return 0;
123}
124
125static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
126{
127 switch (counter_index) {
128 case 0:
129 return NITIO_G0_Command_Reg;
130 break;
131 case 1:
132 return NITIO_G1_Command_Reg;
133 break;
134 case 2:
135 return NITIO_G2_Command_Reg;
136 break;
137 case 3:
138 return NITIO_G3_Command_Reg;
139 break;
140 default:
141 BUG();
142 break;
143 }
144 return 0;
145}
146
147static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
148 counter_index)
149{
150 switch (counter_index) {
151 case 0:
152 return NITIO_G0_Counting_Mode_Reg;
153 break;
154 case 1:
155 return NITIO_G1_Counting_Mode_Reg;
156 break;
157 case 2:
158 return NITIO_G2_Counting_Mode_Reg;
159 break;
160 case 3:
161 return NITIO_G3_Counting_Mode_Reg;
162 break;
163 default:
164 BUG();
165 break;
166 }
167 return 0;
168}
169
170static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
171 counter_index)
172{
173 switch (counter_index) {
174 case 0:
175 return NITIO_G0_Input_Select_Reg;
176 break;
177 case 1:
178 return NITIO_G1_Input_Select_Reg;
179 break;
180 case 2:
181 return NITIO_G2_Input_Select_Reg;
182 break;
183 case 3:
184 return NITIO_G3_Input_Select_Reg;
185 break;
186 default:
187 BUG();
188 break;
189 }
190 return 0;
191}
192
193static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
194 counter_index)
195{
196 switch (counter_index) {
197 case 0:
198 case 1:
199 return NITIO_G01_Joint_Reset_Reg;
200 break;
201 case 2:
202 case 3:
203 return NITIO_G23_Joint_Reset_Reg;
204 break;
205 default:
206 BUG();
207 break;
208 }
209 return 0;
210}
211
212static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
213 counter_index)
214{
215 switch (counter_index) {
216 case 0:
217 case 1:
218 return NITIO_G01_Joint_Status1_Reg;
219 break;
220 case 2:
221 case 3:
222 return NITIO_G23_Joint_Status1_Reg;
223 break;
224 default:
225 BUG();
226 break;
227 }
228 return 0;
229}
230
231static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
232 counter_index)
233{
234 switch (counter_index) {
235 case 0:
236 case 1:
237 return NITIO_G01_Joint_Status2_Reg;
238 break;
239 case 2:
240 case 3:
241 return NITIO_G23_Joint_Status2_Reg;
242 break;
243 default:
244 BUG();
245 break;
246 }
247 return 0;
248}
249
250static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
251{
252 switch (counter_index) {
253 case 0:
254 case 1:
255 return NITIO_G01_Status_Reg;
256 break;
257 case 2:
258 case 3:
259 return NITIO_G23_Status_Reg;
260 break;
261 default:
262 BUG();
263 break;
264 }
265 return 0;
266}
267
268static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
269{
270 switch (counter_index) {
271 case 0:
272 return NITIO_G0_LoadA_Reg;
273 break;
274 case 1:
275 return NITIO_G1_LoadA_Reg;
276 break;
277 case 2:
278 return NITIO_G2_LoadA_Reg;
279 break;
280 case 3:
281 return NITIO_G3_LoadA_Reg;
282 break;
283 default:
284 BUG();
285 break;
286 }
287 return 0;
288}
289
290static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
291{
292 switch (counter_index) {
293 case 0:
294 return NITIO_G0_LoadB_Reg;
295 break;
296 case 1:
297 return NITIO_G1_LoadB_Reg;
298 break;
299 case 2:
300 return NITIO_G2_LoadB_Reg;
301 break;
302 case 3:
303 return NITIO_G3_LoadB_Reg;
304 break;
305 default:
306 BUG();
307 break;
308 }
309 return 0;
310}
311
312static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
313{
314 switch (counter_index) {
315 case 0:
316 return NITIO_G0_Mode_Reg;
317 break;
318 case 1:
319 return NITIO_G1_Mode_Reg;
320 break;
321 case 2:
322 return NITIO_G2_Mode_Reg;
323 break;
324 case 3:
325 return NITIO_G3_Mode_Reg;
326 break;
327 default:
328 BUG();
329 break;
330 }
331 return 0;
332}
333
334static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
335{
336 switch (counter_index) {
337 case 0:
338 return NITIO_G0_SW_Save_Reg;
339 break;
340 case 1:
341 return NITIO_G1_SW_Save_Reg;
342 break;
343 case 2:
344 return NITIO_G2_SW_Save_Reg;
345 break;
346 case 3:
347 return NITIO_G3_SW_Save_Reg;
348 break;
349 default:
350 BUG();
351 break;
352 }
353 return 0;
354}
355
356static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
357{
358 switch (counter_index) {
359 case 0:
360 return NITIO_G0_Second_Gate_Reg;
361 break;
362 case 1:
363 return NITIO_G1_Second_Gate_Reg;
364 break;
365 case 2:
366 return NITIO_G2_Second_Gate_Reg;
367 break;
368 case 3:
369 return NITIO_G3_Second_Gate_Reg;
370 break;
371 default:
372 BUG();
373 break;
374 }
375 return 0;
376}
377
378static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
379{
380 switch (counter_index) {
381 case 0:
382 return NITIO_G0_DMA_Config_Reg;
383 break;
384 case 1:
385 return NITIO_G1_DMA_Config_Reg;
386 break;
387 case 2:
388 return NITIO_G2_DMA_Config_Reg;
389 break;
390 case 3:
391 return NITIO_G3_DMA_Config_Reg;
392 break;
393 default:
394 BUG();
395 break;
396 }
397 return 0;
398}
399
400static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
401{
402 switch (counter_index) {
403 case 0:
404 return NITIO_G0_DMA_Status_Reg;
405 break;
406 case 1:
407 return NITIO_G1_DMA_Status_Reg;
408 break;
409 case 2:
410 return NITIO_G2_DMA_Status_Reg;
411 break;
412 case 3:
413 return NITIO_G3_DMA_Status_Reg;
414 break;
415 default:
416 BUG();
417 break;
418 }
419 return 0;
420}
421
422static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
423{
424 switch (counter_index) {
425 case 0:
426 return NITIO_G0_ABZ_Reg;
427 break;
428 case 1:
429 return NITIO_G1_ABZ_Reg;
430 break;
431 default:
432 BUG();
433 break;
434 }
435 return 0;
436}
437
438static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(int
439 counter_index)
440{
441 switch (counter_index) {
442 case 0:
443 return NITIO_G0_Interrupt_Acknowledge_Reg;
444 break;
445 case 1:
446 return NITIO_G1_Interrupt_Acknowledge_Reg;
447 break;
448 case 2:
449 return NITIO_G2_Interrupt_Acknowledge_Reg;
450 break;
451 case 3:
452 return NITIO_G3_Interrupt_Acknowledge_Reg;
453 break;
454 default:
455 BUG();
456 break;
457 }
458 return 0;
459}
460
461static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
462{
463 switch (counter_index) {
464 case 0:
465 return NITIO_G0_Status_Reg;
466 break;
467 case 1:
468 return NITIO_G1_Status_Reg;
469 break;
470 case 2:
471 return NITIO_G2_Status_Reg;
472 break;
473 case 3:
474 return NITIO_G3_Status_Reg;
475 break;
476 default:
477 BUG();
478 break;
479 }
480 return 0;
481}
482
483static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(int
484 counter_index)
485{
486 switch (counter_index) {
487 case 0:
488 return NITIO_G0_Interrupt_Enable_Reg;
489 break;
490 case 1:
491 return NITIO_G1_Interrupt_Enable_Reg;
492 break;
493 case 2:
494 return NITIO_G2_Interrupt_Enable_Reg;
495 break;
496 case 3:
497 return NITIO_G3_Interrupt_Enable_Reg;
498 break;
499 default:
500 BUG();
501 break;
502 }
503 return 0;
504}
505
506enum ni_gpct_variant {
507 ni_gpct_variant_e_series,
508 ni_gpct_variant_m_series,
509 ni_gpct_variant_660x
510};
511
512struct ni_gpct {
513 struct ni_gpct_device *counter_dev;
514 unsigned counter_index;
515 unsigned chip_index;
516 uint64_t clock_period_ps; /* clock period in picoseconds */
517 struct mite_channel *mite_chan;
518 rtdm_lock_t lock;
519};
520
521struct ni_gpct_device {
522 struct a4l_device *dev;
523 void (*write_register)(struct ni_gpct * counter,
524 unsigned int bits, enum ni_gpct_register reg);
525 unsigned (*read_register)(struct ni_gpct * counter,
526 enum ni_gpct_register reg);
527 enum ni_gpct_variant variant;
528 struct ni_gpct **counters;
529 unsigned num_counters;
530 unsigned regs[NITIO_Num_Registers];
531 rtdm_lock_t regs_lock;
532};
533
534#define Gi_Auto_Increment_Mask 0xff
535#define Gi_Up_Down_Shift 5
536
537#define Gi_Arm_Bit 0x1
538#define Gi_Save_Trace_Bit 0x2
539#define Gi_Load_Bit 0x4
540#define Gi_Disarm_Bit 0x10
541#define Gi_Up_Down_Mask (0x3 << Gi_Up_Down_Shift)
542#define Gi_Always_Down_Bits (0x0 << Gi_Up_Down_Shift)
543#define Gi_Always_Up_Bits (0x1 << Gi_Up_Down_Shift)
544#define Gi_Up_Down_Hardware_IO_Bits (0x2 << Gi_Up_Down_Shift)
545#define Gi_Up_Down_Hardware_Gate_Bits (0x3 << Gi_Up_Down_Shift)
546#define Gi_Write_Switch_Bit 0x80
547#define Gi_Synchronize_Gate_Bit 0x100
548#define Gi_Little_Big_Endian_Bit 0x200
549#define Gi_Bank_Switch_Start_Bit 0x400
550#define Gi_Bank_Switch_Mode_Bit 0x800
551#define Gi_Bank_Switch_Enable_Bit 0x1000
552#define Gi_Arm_Copy_Bit 0x2000
553#define Gi_Save_Trace_Copy_Bit 0x4000
554#define Gi_Disarm_Copy_Bit 0x8000
555
556#define Gi_Index_Phase_Bitshift 5
557#define Gi_HW_Arm_Select_Shift 8
558
559#define Gi_Counting_Mode_Mask 0x7
560#define Gi_Counting_Mode_Normal_Bits 0x0
561#define Gi_Counting_Mode_QuadratureX1_Bits 0x1
562#define Gi_Counting_Mode_QuadratureX2_Bits 0x2
563#define Gi_Counting_Mode_QuadratureX4_Bits 0x3
564#define Gi_Counting_Mode_Two_Pulse_Bits 0x4
565#define Gi_Counting_Mode_Sync_Source_Bits 0x6
566#define Gi_Index_Mode_Bit 0x10
567#define Gi_Index_Phase_Mask (0x3 << Gi_Index_Phase_Bitshift)
568#define Gi_Index_Phase_LowA_LowB (0x0 << Gi_Index_Phase_Bitshift)
569#define Gi_Index_Phase_LowA_HighB (0x1 << Gi_Index_Phase_Bitshift)
570#define Gi_Index_Phase_HighA_LowB (0x2 << Gi_Index_Phase_Bitshift)
571#define Gi_Index_Phase_HighA_HighB (0x3 << Gi_Index_Phase_Bitshift)
572
573/* From m-series example code,
574 not documented in 660x register level manual */
575#define Gi_HW_Arm_Enable_Bit 0x80
576/* From m-series example code,
577 not documented in 660x register level manual */
578#define Gi_660x_HW_Arm_Select_Mask (0x7 << Gi_HW_Arm_Select_Shift)
579#define Gi_660x_Prescale_X8_Bit 0x1000
580#define Gi_M_Series_Prescale_X8_Bit 0x2000
581#define Gi_M_Series_HW_Arm_Select_Mask (0x1f << Gi_HW_Arm_Select_Shift)
582/* Must be set for clocks over 40MHz,
583 which includes synchronous counting and quadrature modes */
584#define Gi_660x_Alternate_Sync_Bit 0x2000
585#define Gi_M_Series_Alternate_Sync_Bit 0x4000
586/* From m-series example code,
587 not documented in 660x register level manual */
588#define Gi_660x_Prescale_X2_Bit 0x4000
589#define Gi_M_Series_Prescale_X2_Bit 0x8000
590
591static inline unsigned int Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
592{
593 switch (variant) {
594 case ni_gpct_variant_e_series:
595 return 0;
596 break;
597 case ni_gpct_variant_m_series:
598 return Gi_M_Series_Alternate_Sync_Bit;
599 break;
600 case ni_gpct_variant_660x:
601 return Gi_660x_Alternate_Sync_Bit;
602 break;
603 default:
604 BUG();
605 break;
606 }
607 return 0;
608}
609
610static inline unsigned int Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
611{
612 switch (variant) {
613 case ni_gpct_variant_e_series:
614 return 0;
615 break;
616 case ni_gpct_variant_m_series:
617 return Gi_M_Series_Prescale_X2_Bit;
618 break;
619 case ni_gpct_variant_660x:
620 return Gi_660x_Prescale_X2_Bit;
621 break;
622 default:
623 BUG();
624 break;
625 }
626 return 0;
627}
628
629static inline unsigned int Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
630{
631 switch (variant) {
632 case ni_gpct_variant_e_series:
633 return 0;
634 break;
635 case ni_gpct_variant_m_series:
636 return Gi_M_Series_Prescale_X8_Bit;
637 break;
638 case ni_gpct_variant_660x:
639 return Gi_660x_Prescale_X8_Bit;
640 break;
641 default:
642 BUG();
643 break;
644 }
645 return 0;
646}
647
648static inline unsigned int Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
649{
650 switch (variant) {
651 case ni_gpct_variant_e_series:
652 return 0;
653 break;
654 case ni_gpct_variant_m_series:
655 return Gi_M_Series_HW_Arm_Select_Mask;
656 break;
657 case ni_gpct_variant_660x:
658 return Gi_660x_HW_Arm_Select_Mask;
659 break;
660 default:
661 BUG();
662 break;
663 }
664 return 0;
665}
666
667#define NI_660x_Timebase_1_Clock 0x0 /* 20MHz */
668#define NI_660x_Source_Pin_i_Clock 0x1
669#define NI_660x_Next_Gate_Clock 0xa
670#define NI_660x_Timebase_2_Clock 0x12 /* 100KHz */
671#define NI_660x_Next_TC_Clock 0x13
672#define NI_660x_Timebase_3_Clock 0x1e /* 80MHz */
673#define NI_660x_Logic_Low_Clock 0x1f
674
675#define ni_660x_max_rtsi_channel 6
676#define ni_660x_max_source_pin 7
677
678static inline unsigned int NI_660x_RTSI_Clock(unsigned int n)
679{
680 BUG_ON(n > ni_660x_max_rtsi_channel);
681 return (0xb + n);
682}
683
684static inline unsigned int NI_660x_Source_Pin_Clock(unsigned int n)
685{
686 BUG_ON(n > ni_660x_max_source_pin);
687 return (0x2 + n);
688}
689
690/* Clock sources for ni e and m series boards,
691 get bits with Gi_Source_Select_Bits() */
692#define NI_M_Series_Timebase_1_Clock 0x0 /* 20MHz */
693#define NI_M_Series_Timebase_2_Clock 0x12 /* 100KHz */
694#define NI_M_Series_Next_TC_Clock 0x13
695#define NI_M_Series_Next_Gate_Clock 0x14 /* when Gi_Src_SubSelect = 0 */
696#define NI_M_Series_PXI_Star_Trigger_Clock 0x14 /* when Gi_Src_SubSelect = 1 */
697#define NI_M_Series_PXI10_Clock 0x1d
698#define NI_M_Series_Timebase_3_Clock 0x1e /* 80MHz, when Gi_Src_SubSelect = 0 */
699#define NI_M_Series_Analog_Trigger_Out_Clock 0x1e /* when Gi_Src_SubSelect = 1 */
700#define NI_M_Series_Logic_Low_Clock 0x1f
701
702#define ni_m_series_max_pfi_channel 15
703#define ni_m_series_max_rtsi_channel 7
704
705static inline unsigned int NI_M_Series_PFI_Clock(unsigned int n)
706{
707 BUG_ON(n > ni_m_series_max_pfi_channel);
708 if (n < 10)
709 return 1 + n;
710 else
711 return 0xb + n;
712}
713
714static inline unsigned int NI_M_Series_RTSI_Clock(unsigned int n)
715{
716 BUG_ON(n > ni_m_series_max_rtsi_channel);
717 if (n == 7)
718 return 0x1b;
719 else
720 return 0xb + n;
721}
722
723#define NI_660x_Source_Pin_i_Gate_Select 0x0
724#define NI_660x_Gate_Pin_i_Gate_Select 0x1
725#define NI_660x_Next_SRC_Gate_Select 0xa
726#define NI_660x_Next_Out_Gate_Select 0x14
727#define NI_660x_Logic_Low_Gate_Select 0x1f
728#define ni_660x_max_gate_pin 7
729
730static inline unsigned int NI_660x_Gate_Pin_Gate_Select(unsigned int n)
731{
732 BUG_ON(n > ni_660x_max_gate_pin);
733 return 0x2 + n;
734}
735
736static inline unsigned int NI_660x_RTSI_Gate_Select(unsigned int n)
737{
738 BUG_ON(n > ni_660x_max_rtsi_channel);
739 return 0xb + n;
740}
741
742
743#define NI_M_Series_Timestamp_Mux_Gate_Select 0x0
744#define NI_M_Series_AI_START2_Gate_Select 0x12
745#define NI_M_Series_PXI_Star_Trigger_Gate_Select 0x13
746#define NI_M_Series_Next_Out_Gate_Select 0x14
747#define NI_M_Series_AI_START1_Gate_Select 0x1c
748#define NI_M_Series_Next_SRC_Gate_Select 0x1d
749#define NI_M_Series_Analog_Trigger_Out_Gate_Select 0x1e
750#define NI_M_Series_Logic_Low_Gate_Select 0x1f
751
752static inline unsigned int NI_M_Series_RTSI_Gate_Select(unsigned int n)
753{
754 BUG_ON(n > ni_m_series_max_rtsi_channel);
755 if (n == 7)
756 return 0x1b;
757 return 0xb + n;
758}
759
760static inline unsigned int NI_M_Series_PFI_Gate_Select(unsigned int n)
761{
762 BUG_ON(n > ni_m_series_max_pfi_channel);
763 if (n < 10)
764 return 1 + n;
765 return 0xb + n;
766}
767
768
769#define Gi_Source_Select_Shift 2
770#define Gi_Gate_Select_Shift 7
771
772#define Gi_Read_Acknowledges_Irq 0x1 /* not present on 660x */
773#define Gi_Write_Acknowledges_Irq 0x2 /* not present on 660x */
774#define Gi_Source_Select_Mask 0x7c
775#define Gi_Gate_Select_Mask (0x1f << Gi_Gate_Select_Shift)
776#define Gi_Gate_Select_Load_Source_Bit 0x1000
777#define Gi_Or_Gate_Bit 0x2000
778#define Gi_Output_Polarity_Bit 0x4000 /* set to invert */
779#define Gi_Source_Polarity_Bit 0x8000 /* set to invert */
780
781#define Gi_Source_Select_Bits(x) ((x << Gi_Source_Select_Shift) & \
782 Gi_Source_Select_Mask)
783#define Gi_Gate_Select_Bits(x) ((x << Gi_Gate_Select_Shift) & \
784 Gi_Gate_Select_Mask)
785
786#define Gi_Gating_Mode_Mask 0x3
787#define Gi_Gating_Disabled_Bits 0x0
788#define Gi_Level_Gating_Bits 0x1
789#define Gi_Rising_Edge_Gating_Bits 0x2
790#define Gi_Falling_Edge_Gating_Bits 0x3
791#define Gi_Gate_On_Both_Edges_Bit 0x4 /* used in conjunction with
792 rising edge gating mode */
793#define Gi_Trigger_Mode_for_Edge_Gate_Mask 0x18
794#define Gi_Edge_Gate_Starts_Stops_Bits 0x0
795#define Gi_Edge_Gate_Stops_Starts_Bits 0x8
796#define Gi_Edge_Gate_Starts_Bits 0x10
797#define Gi_Edge_Gate_No_Starts_or_Stops_Bits 0x18
798#define Gi_Stop_Mode_Mask 0x60
799#define Gi_Stop_on_Gate_Bits 0x00
800#define Gi_Stop_on_Gate_or_TC_Bits 0x20
801#define Gi_Stop_on_Gate_or_Second_TC_Bits 0x40
802#define Gi_Load_Source_Select_Bit 0x80
803#define Gi_Output_Mode_Mask 0x300
804#define Gi_Output_TC_Pulse_Bits 0x100
805#define Gi_Output_TC_Toggle_Bits 0x200
806#define Gi_Output_TC_or_Gate_Toggle_Bits 0x300
807#define Gi_Counting_Once_Mask 0xc00
808#define Gi_No_Hardware_Disarm_Bits 0x000
809#define Gi_Disarm_at_TC_Bits 0x400
810#define Gi_Disarm_at_Gate_Bits 0x800
811#define Gi_Disarm_at_TC_or_Gate_Bits 0xc00
812#define Gi_Loading_On_TC_Bit 0x1000
813#define Gi_Gate_Polarity_Bit 0x2000
814#define Gi_Loading_On_Gate_Bit 0x4000
815#define Gi_Reload_Source_Switching_Bit 0x8000
816
817#define NI_660x_Source_Pin_i_Second_Gate_Select 0x0
818#define NI_660x_Up_Down_Pin_i_Second_Gate_Select 0x1
819#define NI_660x_Next_SRC_Second_Gate_Select 0xa
820#define NI_660x_Next_Out_Second_Gate_Select 0x14
821#define NI_660x_Selected_Gate_Second_Gate_Select 0x1e
822#define NI_660x_Logic_Low_Second_Gate_Select 0x1f
823
824#define ni_660x_max_up_down_pin 7
825
826static inline
827unsigned int NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned int n)
828{
829 BUG_ON(n > ni_660x_max_up_down_pin);
830 return 0x2 + n;
831}
832static inline
833unsigned int NI_660x_RTSI_Second_Gate_Select(unsigned int n)
834{
835 BUG_ON(n > ni_660x_max_rtsi_channel);
836 return 0xb + n;
837}
838
839#define Gi_Second_Gate_Select_Shift 7
840
841/*FIXME: m-series has a second gate subselect bit */
842/*FIXME: m-series second gate sources are undocumented (by NI)*/
843#define Gi_Second_Gate_Mode_Bit 0x1
844#define Gi_Second_Gate_Select_Mask (0x1f << Gi_Second_Gate_Select_Shift)
845#define Gi_Second_Gate_Polarity_Bit 0x2000
846#define Gi_Second_Gate_Subselect_Bit 0x4000 /* m-series only */
847#define Gi_Source_Subselect_Bit 0x8000 /* m-series only */
848
849static inline
850unsigned int Gi_Second_Gate_Select_Bits(unsigned int second_gate_select)
851{
852 return (second_gate_select << Gi_Second_Gate_Select_Shift) &
853 Gi_Second_Gate_Select_Mask;
854}
855
856#define G0_Save_Bit 0x1
857#define G1_Save_Bit 0x2
858#define G0_Counting_Bit 0x4
859#define G1_Counting_Bit 0x8
860#define G0_Next_Load_Source_Bit 0x10
861#define G1_Next_Load_Source_Bit 0x20
862#define G0_Stale_Data_Bit 0x40
863#define G1_Stale_Data_Bit 0x80
864#define G0_Armed_Bit 0x100
865#define G1_Armed_Bit 0x200
866#define G0_No_Load_Between_Gates_Bit 0x400
867#define G1_No_Load_Between_Gates_Bit 0x800
868#define G0_TC_Error_Bit 0x1000
869#define G1_TC_Error_Bit 0x2000
870#define G0_Gate_Error_Bit 0x4000
871#define G1_Gate_Error_Bit 0x8000
872
873static inline unsigned int Gi_Counting_Bit(unsigned int counter_index)
874{
875 if (counter_index % 2)
876 return G1_Counting_Bit;
877 return G0_Counting_Bit;
878}
879
880static inline unsigned int Gi_Armed_Bit(unsigned int counter_index)
881{
882 if (counter_index % 2)
883 return G1_Armed_Bit;
884 return G0_Armed_Bit;
885}
886
887static inline unsigned int Gi_Next_Load_Source_Bit(unsigned counter_index)
888{
889 if (counter_index % 2)
890 return G1_Next_Load_Source_Bit;
891 return G0_Next_Load_Source_Bit;
892}
893
894static inline unsigned int Gi_Stale_Data_Bit(unsigned int counter_index)
895{
896 if (counter_index % 2)
897 return G1_Stale_Data_Bit;
898 return G0_Stale_Data_Bit;
899}
900
901static inline unsigned int Gi_TC_Error_Bit(unsigned int counter_index)
902{
903 if (counter_index % 2)
904 return G1_TC_Error_Bit;
905 return G0_TC_Error_Bit;
906}
907
908static inline unsigned int Gi_Gate_Error_Bit(unsigned int counter_index)
909{
910 if (counter_index % 2)
911 return G1_Gate_Error_Bit;
912 return G0_Gate_Error_Bit;
913}
914
915/* Joint reset register bits */
916static inline unsigned Gi_Reset_Bit(unsigned int counter_index)
917{
918 return 0x1 << (2 + (counter_index % 2));
919}
920
921#define G0_Output_Bit 0x1
922#define G1_Output_Bit 0x2
923#define G0_HW_Save_Bit 0x1000
924#define G1_HW_Save_Bit 0x2000
925#define G0_Permanent_Stale_Bit 0x4000
926#define G1_Permanent_Stale_Bit 0x8000
927
928static inline unsigned int Gi_Permanent_Stale_Bit(unsigned
929 counter_index)
930{
931 if (counter_index % 2)
932 return G1_Permanent_Stale_Bit;
933 return G0_Permanent_Stale_Bit;
934}
935
936#define Gi_DMA_Enable_Bit 0x1
937#define Gi_DMA_Write_Bit 0x2
938#define Gi_DMA_Int_Bit 0x4
939
940#define Gi_DMA_Readbank_Bit 0x2000
941#define Gi_DRQ_Error_Bit 0x4000
942#define Gi_DRQ_Status_Bit 0x8000
943
944#define G0_Gate_Error_Confirm_Bit 0x20
945#define G0_TC_Error_Confirm_Bit 0x40
946
947#define G1_Gate_Error_Confirm_Bit 0x2
948#define G1_TC_Error_Confirm_Bit 0x4
949
950static inline unsigned int Gi_Gate_Error_Confirm_Bit(unsigned int counter_index)
951{
952 if (counter_index % 2)
953 return G1_Gate_Error_Confirm_Bit;
954 return G0_Gate_Error_Confirm_Bit;
955}
956
957static inline unsigned int Gi_TC_Error_Confirm_Bit(unsigned int counter_index)
958{
959 if (counter_index % 2)
960 return G1_TC_Error_Confirm_Bit;
961 return G0_TC_Error_Confirm_Bit;
962}
963
964/* Bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
965#define Gi_TC_Interrupt_Ack_Bit 0x4000
966#define Gi_Gate_Interrupt_Ack_Bit 0x8000
967
968#define Gi_Gate_Interrupt_Bit 0x4
969#define Gi_TC_Bit 0x8
970#define Gi_Interrupt_Bit 0x8000
971
972#define G0_TC_Interrupt_Enable_Bit 0x40
973#define G0_Gate_Interrupt_Enable_Bit 0x100
974
975#define G1_TC_Interrupt_Enable_Bit 0x200
976#define G1_Gate_Interrupt_Enable_Bit 0x400
977
978static inline unsigned int Gi_Gate_Interrupt_Enable_Bit(unsigned int counter_index)
979{
980 unsigned int bit;
981
982 if (counter_index % 2) {
983 bit = G1_Gate_Interrupt_Enable_Bit;
984 } else {
985 bit = G0_Gate_Interrupt_Enable_Bit;
986 }
987 return bit;
988}
989
990#define counter_status_mask (A4L_COUNTER_ARMED | A4L_COUNTER_COUNTING)
991
992#define NI_USUAL_PFI_SELECT(x) ((x < 10) ? (0x1 + x) : (0xb + x))
993#define NI_USUAL_RTSI_SELECT(x) ((x < 7 ) ? (0xb + x) : (0x1b + x))
994
995/* Mode bits for NI general-purpose counters, set with
996 INSN_CONFIG_SET_COUNTER_MODE */
997#define NI_GPCT_COUNTING_MODE_SHIFT 16
998#define NI_GPCT_INDEX_PHASE_BITSHIFT 20
999#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
1000
1001#define NI_GPCT_GATE_ON_BOTH_EDGES_BIT 0x4
1002#define NI_GPCT_EDGE_GATE_MODE_MASK 0x18
1003#define NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS 0x0
1004#define NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS 0x8
1005#define NI_GPCT_EDGE_GATE_STARTS_BITS 0x10
1006#define NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS 0x18
1007#define NI_GPCT_STOP_MODE_MASK 0x60
1008#define NI_GPCT_STOP_ON_GATE_BITS 0x00
1009#define NI_GPCT_STOP_ON_GATE_OR_TC_BITS 0x20
1010#define NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS 0x40
1011#define NI_GPCT_LOAD_B_SELECT_BIT 0x80
1012#define NI_GPCT_OUTPUT_MODE_MASK 0x300
1013#define NI_GPCT_OUTPUT_TC_PULSE_BITS 0x100
1014#define NI_GPCT_OUTPUT_TC_TOGGLE_BITS 0x200
1015#define NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS 0x300
1016#define NI_GPCT_HARDWARE_DISARM_MASK 0xc00
1017#define NI_GPCT_NO_HARDWARE_DISARM_BITS 0x000
1018#define NI_GPCT_DISARM_AT_TC_BITS 0x400
1019#define NI_GPCT_DISARM_AT_GATE_BITS 0x800
1020#define NI_GPCT_DISARM_AT_TC_OR_GATE_BITS 0xc00
1021#define NI_GPCT_LOADING_ON_TC_BIT 0x1000
1022#define NI_GPCT_LOADING_ON_GATE_BIT 0x4000
1023#define NI_GPCT_COUNTING_MODE_MASK 0x7 << NI_GPCT_COUNTING_MODE_SHIFT
1024#define NI_GPCT_COUNTING_MODE_NORMAL_BITS 0x0 << NI_GPCT_COUNTING_MODE_SHIFT
1025#define NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS 0x1 << NI_GPCT_COUNTING_MODE_SHIFT
1026#define NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS 0x2 << NI_GPCT_COUNTING_MODE_SHIFT
1027#define NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS 0x3 << NI_GPCT_COUNTING_MODE_SHIFT
1028#define NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS 0x4 << NI_GPCT_COUNTING_MODE_SHIFT
1029#define NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS 0x6 << NI_GPCT_COUNTING_MODE_SHIFT
1030#define NI_GPCT_INDEX_PHASE_MASK 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT
1031#define NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT
1032#define NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT
1033#define NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT
1034#define NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT
1035#define NI_GPCT_INDEX_ENABLE_BIT 0x400000
1036#define NI_GPCT_COUNTING_DIRECTION_MASK 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1037#define NI_GPCT_COUNTING_DIRECTION_DOWN_BITS 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1038#define NI_GPCT_COUNTING_DIRECTION_UP_BITS 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1039#define NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1040#define NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1041#define NI_GPCT_RELOAD_SOURCE_MASK 0xc000000
1042#define NI_GPCT_RELOAD_SOURCE_FIXED_BITS 0x0
1043#define NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS 0x4000000
1044#define NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS 0x8000000
1045#define NI_GPCT_OR_GATE_BIT 0x10000000
1046#define NI_GPCT_INVERT_OUTPUT_BIT 0x20000000
1047
1048/* Bits for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC when
1049 using NI general-purpose counters. */
1050#define NI_GPCT_CLOCK_SRC_SELECT_MASK 0x3f
1051#define NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS 0x0
1052#define NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS 0x1
1053#define NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS 0x2
1054#define NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS 0x3
1055#define NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS 0x4
1056#define NI_GPCT_NEXT_TC_CLOCK_SRC_BITS 0x5
1057#define NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS 0x6 /* NI 660x-specific */
1058#define NI_GPCT_PXI10_CLOCK_SRC_BITS 0x7
1059#define NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS 0x8
1060#define NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS 0x9
1061#define NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK 0x30000000
1062#define NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS 0x0
1063#define NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS 0x10000000 /* divide source by 2 */
1064#define NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS 0x20000000 /* divide source by 8 */
1065#define NI_GPCT_INVERT_CLOCK_SRC_BIT 0x80000000
1066#define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x) (0x10 + x)
1067#define NI_GPCT_RTSI_CLOCK_SRC_BITS(x) (0x18 + x)
1068#define NI_GPCT_PFI_CLOCK_SRC_BITS(x) (0x20 + x)
1069
1070/* Possibilities for setting a gate source with
1071 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
1072 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
1073/* M-series gates */
1074#define NI_GPCT_TIMESTAMP_MUX_GATE_SELECT 0x0
1075#define NI_GPCT_AI_START2_GATE_SELECT 0x12
1076#define NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT 0x13
1077#define NI_GPCT_NEXT_OUT_GATE_SELECT 0x14
1078#define NI_GPCT_AI_START1_GATE_SELECT 0x1c
1079#define NI_GPCT_NEXT_SOURCE_GATE_SELECT 0x1d
1080#define NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT 0x1e
1081#define NI_GPCT_LOGIC_LOW_GATE_SELECT 0x1f
1082/* More gates for 660x */
1083#define NI_GPCT_SOURCE_PIN_i_GATE_SELECT 0x100
1084#define NI_GPCT_GATE_PIN_i_GATE_SELECT 0x101
1085/* More gates for 660x "second gate" */
1086#define NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT 0x201
1087#define NI_GPCT_SELECTED_GATE_GATE_SELECT 0x21e
1088/* M-series "second gate" sources are unknown, we should add them here
1089 with an offset of 0x300 when known. */
1090#define NI_GPCT_DISABLED_GATE_SELECT 0x8000
1091#define NI_GPCT_GATE_PIN_GATE_SELECT(x) (0x102 + x)
1092#define NI_GPCT_RTSI_GATE_SELECT(x) NI_USUAL_RTSI_SELECT(x)
1093#define NI_GPCT_PFI_GATE_SELECT(x) NI_USUAL_PFI_SELECT(x)
1094#define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x) (0x202 + x)
1095
1096/* Possibilities for setting a source with INSN_CONFIG_SET_OTHER_SRC
1097 when using NI general-purpose counters. */
1098#define NI_GPCT_SOURCE_ENCODER_A 0
1099#define NI_GPCT_SOURCE_ENCODER_B 1
1100#define NI_GPCT_SOURCE_ENCODER_Z 2
1101/* M-series gates */
1102/* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
1103#define NI_GPCT_DISABLED_OTHER_SELECT 0x8000
1104#define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x)
1105
1106/* Start sources for ni general-purpose counters for use with
1107 INSN_CONFIG_ARM */
1108#define NI_GPCT_ARM_IMMEDIATE 0x0
1109/* Start both the counter and the adjacent paired counter
1110 simultaneously */
1111#define NI_GPCT_ARM_PAIRED_IMMEDIATE 0x1
1112/* NI doesn't document bits for selecting hardware arm triggers. If
1113 the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least significant
1114 bits (3 bits for 660x or 5 bits for m-series) through to the
1115 hardware. This will at least allow someone to figure out what the bits
1116 do later. */
1117#define NI_GPCT_ARM_UNKNOWN 0x1000
1118
1119/* Digital filtering options for ni 660x for use with
1120 INSN_CONFIG_FILTER. */
1121#define NI_GPCT_FILTER_OFF 0x0
1122#define NI_GPCT_FILTER_TIMEBASE_3_SYNC 0x1
1123#define NI_GPCT_FILTER_100x_TIMEBASE_1 0x2
1124#define NI_GPCT_FILTER_20x_TIMEBASE_1 0x3
1125#define NI_GPCT_FILTER_10x_TIMEBASE_1 0x4
1126#define NI_GPCT_FILTER_2x_TIMEBASE_1 0x5
1127#define NI_GPCT_FILTER_2x_TIMEBASE_3 0x6
1128
1129/* Master clock sources for ni mio boards and
1130 INSN_CONFIG_SET_CLOCK_SRC */
1131#define NI_MIO_INTERNAL_CLOCK 0
1132#define NI_MIO_RTSI_CLOCK 1
1133/* Doesn't work for m-series, use NI_MIO_PLL_RTSI_CLOCK() the
1134 NI_MIO_PLL_* sources are m-series only */
1135#define NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK 2
1136#define NI_MIO_PLL_PXI10_CLOCK 3
1137#define NI_MIO_PLL_RTSI0_CLOCK 4
1138
1139#define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x))
1140
1141/* Signals which can be routed to an NI RTSI pin with
1142 INSN_CONFIG_SET_ROUTING. The numbers assigned are not arbitrary, they
1143 correspond to the bits required to program the board. */
1144#define NI_RTSI_OUTPUT_ADR_START1 0
1145#define NI_RTSI_OUTPUT_ADR_START2 1
1146#define NI_RTSI_OUTPUT_SCLKG 2
1147#define NI_RTSI_OUTPUT_DACUPDN 3
1148#define NI_RTSI_OUTPUT_DA_START1 4
1149#define NI_RTSI_OUTPUT_G_SRC0 5
1150#define NI_RTSI_OUTPUT_G_GATE0 6
1151#define NI_RTSI_OUTPUT_RGOUT0 7
1152#define NI_RTSI_OUTPUT_RTSI_BRD_0 8
1153/* Pre-m-series always have RTSI clock on line 7 */
1154#define NI_RTSI_OUTPUT_RTSI_OSC 12
1155
1156#define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x))
1157
1158
1159int a4l_ni_tio_rinsn(struct ni_gpct *counter, struct a4l_kernel_instruction *insn);
1160int a4l_ni_tio_winsn(struct ni_gpct *counter, struct a4l_kernel_instruction *insn);
1161int a4l_ni_tio_insn_config(struct ni_gpct *counter, struct a4l_kernel_instruction *insn);
1162void a4l_ni_tio_init_counter(struct ni_gpct *counter);
1163
1164struct ni_gpct_device *a4l_ni_gpct_device_construct(struct a4l_device * dev,
1165 void (*write_register) (struct ni_gpct * counter, unsigned int bits,
1166 enum ni_gpct_register reg),
1167 unsigned int (*read_register) (struct ni_gpct * counter,
1168 enum ni_gpct_register reg), enum ni_gpct_variant variant,
1169 unsigned int num_counters);
1170void a4l_ni_gpct_device_destroy(struct ni_gpct_device *counter_dev);
1171
1172#if (defined(CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE) || \
1173 defined(CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE_MODULE))
1174
1175extern struct a4l_cmd_desc a4l_ni_tio_cmd_mask;
1176
1177int a4l_ni_tio_input_inttrig(struct ni_gpct *counter, lsampl_t trignum);
1178int a4l_ni_tio_cmd(struct ni_gpct *counter, struct a4l_cmd_desc *cmd);
1179int a4l_ni_tio_cmdtest(struct ni_gpct *counter, struct a4l_cmd_desc *cmd);
1180int a4l_ni_tio_cancel(struct ni_gpct *counter);
1181
1182void a4l_ni_tio_handle_interrupt(struct ni_gpct *counter, struct a4l_device *dev);
1183void a4l_ni_tio_set_mite_channel(struct ni_gpct *counter,
1184 struct mite_channel *mite_chan);
1185void a4l_ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
1186 int *gate_error,
1187 int *tc_error,
1188 int *perm_stale_data, int *stale_data);
1189
1190#endif /* CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE */
1191
1192#endif /* !__ANALOGY_NI_TIO_H__ */
rtdm_lock_t
pipeline_spinlock_t rtdm_lock_t
Lock variable.
Definition driver.h:552
a4l_cmd_desc
Structure describing the asynchronous instruction.
Definition analogy.h:289