Xenomai  3.1
e1000_82541.h
1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2008 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <linux.nics@intel.com>
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_82541_H_
30 #define _E1000_82541_H_
31 
32 #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
33 
34 #define IGP01E1000_PHY_CHANNEL_NUM 4
35 
36 #define IGP01E1000_PHY_AGC_A 0x1172
37 #define IGP01E1000_PHY_AGC_B 0x1272
38 #define IGP01E1000_PHY_AGC_C 0x1472
39 #define IGP01E1000_PHY_AGC_D 0x1872
40 
41 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
42 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
43 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
44 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
45 
46 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
47 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
48 
49 #define IGP01E1000_PHY_DSP_RESET 0x1F33
50 
51 #define IGP01E1000_PHY_DSP_FFE 0x1F35
52 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
53 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
54 
55 #define IGP01E1000_IEEE_FORCE_GIG 0x0140
56 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
57 
58 #define IGP01E1000_AGC_LENGTH_SHIFT 7
59 #define IGP01E1000_AGC_RANGE 10
60 
61 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
62 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
63 
64 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
65 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
66 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
67 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
68 
69 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
70 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
71 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
72 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
73 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
74 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
75 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
76 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
77 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
78 
79 #define IGP01E1000_MSE_CHANNEL_D 0x000F
80 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
81 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
82 #define IGP01E1000_MSE_CHANNEL_A 0xF000
83 
84 #endif